TDA2EX datasheet(146/391 Pages) TI1

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xi_osc1

CK0

CK1

SPRS906_CLK_08

146

TDA2EG-17

SPRS969B – AUGUST 2016 – REVISED JUNE 2017

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Specifications

Table 5-21. OSC1 Input Clock Timing Requirements (continued)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

tj(xiosc1)

Frequency accuracy(2), xi_osc1

Ethernet and MLB not used

±200

ppm

Ethernet RGMII and RMII

using derived clock

±50

Ethernet MII using derived

clock

±100

MLB using derived clock

±50

(1) Period jitter is meant here as follows:

–

The maximum value is the difference between the longest measured clock period and the expected clock period

–

The minimum value is the difference between the shortest measured clock period and the expected clock period

(2) Crystal characteristics should account for tolerance+stability+aging.

(3) The Period jitter requirement for osc1 can be relaxed to 0.02 × tc(xiosc1) under the following constraints:

a.The osc1/SYS_CLK2 clock bypasses all device PLLs

b.The osc1/SYS_CLK2 clock is only used to source the DSS pixel clock outputs

Figure 5-15. xi_osc1 Input Clock

5.9.4.2

Output Clocks

NOTE

NOTE TO USERS:

The content of this section is UNDER DEVELOPMENT!

5.9.4.3

DPLLs, DLLs

NOTE

For more information, see:

•

Power, Reset, and Clock Management / Clock Management Functional / Internal Clock

Sources / Generators / Generic DPLL Overview Section

and

•

Display Subsystem / Display Subsystem Overview section of the Device TRM.

To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the

PRCM module. They are of two types: type A and type B DPLLs.

•

They have their own independent power domain (each one embeds its own switch and can be

controlled as an independent functional power domain)

•

They are fed with ALWAYS ON system clock, with independent control per DPLL.

The different DPLLs managed by the PRCM are listed below:

•

DPLL_MPU: It supplies the MPU subsystem clocking internally.

•

DPLL_IVA: It feeds the IVA subsystem clocking.

•

DPLL_CORE: It supplies all interface clocks and also few module functional clocks.

•

DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock, a

96-MHz functional clock to subsystems and peripherals.

•

DPLL_ABE: It provides clocks to various modules within the device.

•

DPLL_USB: It provides 960M clock for USB modules (USB1/2/3/4).

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