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TDA2EX Datasheet(PDF) 150 Page - Texas Instruments |
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TDA2EX Datasheet(HTML) 150 Page - Texas Instruments |
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150 / 391 page ![]() 150 TDA2EG-17 SPRS969B – AUGUST 2016 – REVISED JUNE 2017 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2EG-17 Specifications Copyright © 2016–2017, Texas Instruments Incorporated 5.9.4.3.3 DPLL and DLL Noise Isolation NOTE For more information on DPLL and DLL decoupling capacitor requirements, see the External Capacitors / Voltage Decoupling Capacitors / I/O and Analog Voltage Decoupling / VDDA Power Domain section. 5.9.5 Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. Monotonic transitions are more easily guaranteed with faster switching signals. Slower input transitions are more susceptible to glitches due to noise and special care should be taken for slow input clocks. 5.9.6 Peripherals 5.9.6.1 Timing Test Conditions All timing requirements and switching characteristics are valid over the recommended operating conditions unless otherwise specified. 5.9.6.2 Virtual and Manual I/O Timing Modes Some of the timings described in the following sections require the use of Virtual or Manual I/O Timing Modes. Table 5-26 provides a summary of the Virtual and Manual I/O Timing Modes across all device interfaces. The individual interface timing sections found later in this document provide the full description of each applicable Virtual and Manual I/O Timing Mode. Refer to the "Pad Configuration" section of the TRM for the procedure on implementing the Virtual and Manual Timing Modes in a system. Table 5-26. Modes Summary Virtual or Manual IO Mode Name Data Manual Timing Mode DPI Video Output No Virtual or Manual IO Timing Mode Required DPI3 Video Output Default Timings - Rising-edge Clock Reference DSS_VIRTUAL1 DPI3 Video Output Default Timings - Falling-edge Clock Reference VOUT2_IOSET1_MANUAL1 DPI2 Video Output IOSET1 Alternate Timings VOUT2_IOSET1_MANUAL2 DPI2 Video Output IOSET1 Default Timings - Rising-edge Clock Reference VOUT2_IOSET1_MANUAL3 DPI2 Video Output IOSET1 Default Timings - Falling-edge Clock Reference VOUT3_MANUAL1 DPI3 Video Output Alternate Timings GPMC No Virtual or Manual IO Timing Mode Required GPMC Asynchronous Mode Timings and Synchronous Mode - Default Timings GPMC_VIRTUAL1 GPMC Synchronous Mode - Alternate Timings McASP No Virtual or Manual IO Timing Mode Required McASP1 Asynchronous and Synchronous Transmit Timings MCASP1_VIRTUAL1_SYNC_RX See Table 5-68 MCASP1_VIRTUAL2_ASYNC_RX See Table 5-68 No Virtual or Manual IO Timing Mode Required McASP2 Asynchronous and Synchronous Transmit Timings MCASP2_VIRTUAL1_SYNC_RX_80M See Table 5-69 MCASP2_VIRTUAL2_ASYNC_RX See Table 5-69 MCASP2_VIRTUAL3_SYNC_RX See Table 5-69 MCASP2_VIRTUAL4_ASYNC_RX_80M See Table 5-69 No Virtual or Manual IO Timing Mode Required McASP3 Synchronous Transmit Timings MCASP3_VIRTUAL2_SYNC_RX See Table 5-70 |
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