TDA2EX datasheet(152/391 Pages) TI1

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vinx_clki

SPRS906_TIMING_VIP_01

152

TDA2EG-17

SPRS969B – AUGUST 2016 – REVISED JUNE 2017

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Specifications

Table 5-26. Modes Summary (continued)

Virtual or Manual IO Mode Name

Data Manual Timing Mode

VIP_MANUAL12

VIN1A (IOSET2/3/4) and VIN1B (IOSET4) and VIN2B (IOSET1/10) Fall-Edge Capture

Mode Timings

VIP_MANUAL14

VIN1B (IOSET6/7) Fall-Edge Capture Mode Timings

VIP_MANUAL15

VIN1A (IOSET8/9/10) Rise-Edge Capture Mode Timings

VIP_MANUAL16

VIN1A (IOSET8/9/10) Fall-Edge Capture Mode Timings

HDMI, EMIF, Timers, I2C, UART, McSPI, USB, PCIe, DCAN, GPIO, PWM, JTAG, TPIU, SDMA, INTC

No Virtual or Manual IO Timing Mode Required

All Modes

5.9.6.3

VIP

The Device includes 1 Video Input Ports (VIP).

Table 5-27, Figure 5-16 and Figure 5-17 present timings and switching characteristics of the VIPs.

CAUTION

The I/O timings provided in this section are valid only for VIN1 and VIN2 if

signals within a single IOSET are used. The IOSETs are defined in Table 5-28.

Table 5-27. Timing Requirements for VIP (3)(4)(5)

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tc(CLK)

Cycle time, vinx_clki (3) (5)

6.06 (2)

tw(CLKH)

Pulse duration, vinx_clki high (3) (5)

0.45 × P

(2)

tw(CLKL)

Pulse duration, vinx_clki low (3) (5)

0.45 × P

(2)

tsu(CTL/DATA-CLK)

Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi,

vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition (3) (4) (5)

3.11 (2)

th(CLK-CTL/DATA)

Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci)

and Data (vinx_dn) valid from vinx_clki transition (3) (4) (5)

-0.05 (2)

(1) For maximum frequency of 165 MHz.

(2) P = vinx_clki period.

(3) x in vinx = 1a, 1b, 2a, 2b.

(4) n in dn = 0 to 7 when x = 1b, 2b.

n = 0 to 23 when x = 1a, 2a.

(5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1.

Figure 5-16. Video Input Ports clock signal

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