PCI7510 datasheet(171/234 Pages) TI

171 / 234 page

8–12

8.14 Posted Write Address High Register

The posted write address high register communicates error information if a write request is posted and an error occurs

while writing the posted data packet. See Table 8–10 for a complete description of the register contents.

Bit

Name

Posted write address high

Type

Default

Bit

Name

Posted write address high

Type

Default

Posted write address high

Offset:

3Ch

Type:

Read/Update

Default:

XXXX XXXXh

Table 8–10. Posted Write Address High Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31–16

sourceID

This field is the 10-bit bus number (bits 31–22) and 6-bit node number (bits 21–16) of the node that

issued the write request that failed.

15–0

offsetHi

The upper 16 bits of the 1394 destination offset of the write request that failed.

8.15 Vendor ID Register

The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers. The

PCI7510 device implements Texas Instruments unique behavior with regards to OHCI. Thus, this register is read-only

and returns 0108 0028h when read.

Bit

Name

Vendor ID

Type

Default

Bit

Name

Vendor ID

Type

Default

Vendor ID

Offset:

40h

Type:

Read-only

Default:

0108 0028h

PCI7510 Datasheet(PDF) 171 Page - Texas Instruments

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