PCI7510 datasheet(174/234 Pages) TI

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8–15

8.18 Self-ID Count Register

The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID

packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 8–12 for a complete description

of the register contents.

Bit

Name

Self-ID count

Type

Default

Bit

Name

Self-ID count

Type

Default

Self-ID count

Offset:

68h

Type:

Read/Update, Read-only

Default:

X0XX 0000h

Table 8–12. Self-ID Count Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

selfIDError

When bit 31 is set to 1, an error was detected during the most recent self-ID packet reception. The

contents of the self-ID buffer are undefined. This bit is cleared after a self-ID reception in which no

errors are detected. Note that an error can be a hardware error or a host bus write error.

30–24

RSVD

Reserved. Bits 30–24 return 0s when read.

23–16

selfIDGeneration

The value in this field increments each time a bus reset is detected. This field rolls over to 0 after

reaching 255.

15–11

RSVD

Reserved. Bits 15–11 return 0s when read.

10–2

selfIDSize

This field indicates the number of quadlets that have been written into the self-ID buffer for the current

bits 23–16 (selfIDGeneration field). This includes the header quadlet and the self-ID data. This field

is cleared to 0s when the self-ID reception begins.

1–0

RSVD

Reserved. Bits 1 and 0 return 0s when read.

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