PCI7510 datasheet(172/234 Pages) TI

172 / 234 page

8–13

8.16 Host Controller Control Register

The host controller control set/clear register pair provides flags for controlling the PCI7510 device. See Table 8–11

for a complete description of the register contents.

Bit

Name

Host controller control

Type

RSU

RSC

RSCU

Default

Bit

Name

Host controller control

Type

Default

Host controller control

Offset:

50h

set register

54h

clear register

Type:

Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read-only

Default:

X08X 0000h

Table 8–11. Host Controller Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

BIBimage Valid

RSU

When bit 31 is set to 1, the PCI7510 physical response unit is enabled to respond to block read

requests to host configuration ROM and to the mechanism for atomically updating configuration

ROM. Software creates a valid image of the bus_info_block in host configuration ROM before

setting this bit.

When this bit is cleared, the PCI7510 device returns ack_type_error on block read requests to

host configuration ROM. Also, when this bit is cleared and a 1394 bus reset occurs, the

configuration ROM mapping register at OHCI offset 34h (see Section 8.12), configuration ROM

header register at OHCI offset 18h (see Section 8.7), and bus options register at OHCI offset 20h

(see Section 8.9) are not updated.

Software can set this bit only when bit 17 (linkEnable) is 0. Once bit 31 is set to 1, it can be cleared

by a system (hardware) reset, a software reset, or if a fetch error occurs when the PCI7510 device

loads bus_info_block registers from host memory.

noByteSwapData

RSC

Bit 30 controls whether physical accesses to locations outside the PCI7510 device itself, as well

as any other DMA data accesses are byte swapped.

AckTardyEnable

RSC

Bit 29 controls the acknowledgement of ack_tardy. When bit 29 is set to 1, ack_tardy may be

returned as an acknowledgment to accesses from the 1394 bus to the PCI7510 device, including

accesses to the bus_info_block. The PCI7510 device returns ack_tardy to all other asynchronous

packets addressed to the PCI7510 node. When the PCI7510 device sends ack_tardy, bit 27

(ack_tardy) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) is set to 1

to indicate the attempted asynchronous access.

Software ensures that bit 27 (ack_tardy) in the interrupt event register is 0. Software also unmasks

wake-up interrupt events such as bit 19 (phy) and bit 27 (ack_tardy) in the interrupt event register

before placing the PCI7510 device into the D1 power mode.

Software must not set this bit if the PCI7510 node is the 1394 bus manager.

28–24

RSVD

Reserved. Bits 28–24 return 0s when read.

23 ‡

programPhyEnable

Bit 23 informs upper-level software that lower-level software has consistently configured the IEEE

1394a-2000 enhancements in the link and PHY layers. When this bit is 1, generic software such

as the OHCI driver is responsible for configuring IEEE 1394a-2000 enhancements in the PHY

layer and bit 22 (aPhyEnhanceEnable). When this bit is 0, the generic software may not modify

the IEEE 1394a-2000 enhancements in the PHY layer and cannot interpret the setting of bit 22

(aPhyEnhanceEnable). This bit is initialized from serial EEPROM. This bit defaults to 1.

‡ One or more bits in this register are cleared only by the assertion of GRST.

PCI7510 Datasheet(PDF) 172 Page - Texas Instruments

PCI7510 Datasheet(HTML) 172 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL