PCI7510 datasheet(180/234 Pages) TI

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8–21

Table 8–16. Interrupt Mask Register Description (Continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

regAccessFail

RSC

When this bit and bit 18 (regAccessFail) in the interrupt event register at OHCI offset 80h/84h (see

Section 8.21) are set to 1, this register-access-failed interrupt mask enables interrupt generation.

busReset

RSC

When this bit and bit 17 (busReset) in the interrupt event register at OHCI offset 80h/84h (see

Section 8.21) are set to 1, this bus-reset interrupt mask enables interrupt generation.

selfIDcomplete

RSC

When this bit and bit 16 (selfIDcomplete) in the interrupt event register at OHCI offset 80h/84h (see

Section 8.21) are set to 1, this self-ID-complete interrupt mask enables interrupt generation.

selfIDcomplete2

RSC

When this bit and bit 15 (selfIDcomplete2) in the interrupt event register at OHCI offset 80h/84h (see

Section 8.21) are set to 1, this second-self-ID-complete interrupt mask enables interrupt generation.

14–10

RSVD

Reserved. Bits 14–10 return 0s when read.

lockRespErr

RSC

When this bit and bit 9 (lockRespErr) in the interrupt event register at OHCI offset 80h/84h (see

Section 8.21) are set to 1, this lock-response-error interrupt mask enables interrupt generation.

postedWriteErr

RSC

When this bit and bit 8 (postedWriteErr) in the interrupt event register at OHCI offset 80h/84h (see

Section 8.21) are set to 1, this posted-write-error interrupt mask enables interrupt generation.

isochRx

RSC

When this bit and bit 7 (isochRx) in the interrupt event register at OHCI offset 80h/84h (see

Section 8.21) are set to 1, this isochronous-receive-DMA interrupt mask enables interrupt generation.

isochTx

RSC

When this bit and bit 6 (isochTx) in the interrupt event register at OHCI offset 80h/84h (see

Section 8.21) are set to 1, this isochronous-transmit-DMA interrupt mask enables interrupt generation.

RSPkt

RSC

When this bit and bit 5 (RSPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21)

are set to 1, this receive-response-packet interrupt mask enables interrupt generation.

RQPkt

RSC

When this bit and bit 4 (RQPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21)

are set to 1, this receive-request-packet interrupt mask enables interrupt generation.

ARRS

RSC

When this bit and bit 3 (ARRS) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21)

are set to 1, this asynchronous-receive-response-DMA interrupt mask enables interrupt generation.

ARRQ

RSC

When this bit and bit 2 (ARRQ) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21)

are set to 1, this asynchronous-receive-request-DMA interrupt mask enables interrupt generation.

respTxComplete

RSC

When this bit and bit 1 (respTxComplete) in the interrupt event register at OHCI offset 80h/84h (see

Section 8.21) are set to 1, this response-transmit-complete interrupt mask enables interrupt

generation.

reqTxComplete

RSC

When this bit and bit 0 (reqTxComplete) in the interrupt event register at OHCI offset 80h/84h (see

Section 8.21) are set to 1, this request-transmit-complete interrupt mask enables interrupt generation.

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