LTC4449 datasheet(59/108 Pages) LINER

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LTC3882-1

Rev A

For more information www.analog.com

Figure 41. Normalized RMS Input Ripple Current

Figure 42. Normalized Output Ripple Current [IRMS ~ 0.3(DIC(PP))]

0.1

0.2

0.3

0.4

38821 F41

0.5

0.6

DUTY FACTOR (VOUT/VIN)

0.1

0.3

0.5 0.6

0.2

0.4

0.7 0.8 0.9

1-PHASE

2-PHASE

DUTY FACTOR (VOUT/VIN)

0.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.3

0.5 0.6

38821 F42

0.2

0.4

0.7 0.8 0.9

1-PHASE

2-PHASE

Figure 40. Single and 2-Phase Current Waveforms

38821 F40

SW1 V

ICIN

ICOUT

SINGLE PHASE

SW1 V

SW2 V

ICIN

IL2

IL1

ICOUT

DUAL PHASE

RIPPLE

synchronizedtime-basedrailsequencingandrampingand

report accurate output current telemetry for all phases.

In general, only the PGOOD pin of the master phase needs

to be used for external Power Good indication. However,

APPLICATIONS INFORMATION

PGOOD pins of slave phases may be shorted to a master

PGOOD bus to indicate full output power is available, un-

less the slave channel is used in active phase shedding.

In that case, the slave PGOOD should be left disconnected

or used only to indicate operating status for that phase.

Output current fault and warning limits should each be set

to the same values across all PolyPhase channels using

IOUT_FAULT_LIMIT and IOUT_WARN_LIMIT. The cor-

rect sense resistance and related temperature coefficient

should also be set for each phase (IOUT_CAL_GAIN,

MFR_IOUT_CAL_GAIN_TC) to achieve accurate IOUT

telemetry and consistent fault handling across phases.

Because the LTC3882-1 current sharing loop operates by

matching sensed voltage, it is important that well-matched

sense elements be used in the system. Current matching

parametersspecifiedfortheLTC3882-1donotincludethese

external sources of error, such as inductor DCR tolerance.

Programming of VOUT related parameters is not required

for slave phases.

APolyPhasepowersupplysignificantlyreducestheamount

of ripple current in both the input and output capacitors.

The RMS input ripple current is divided by, and the ef-

fective ripple frequency is multiplied by, the number of

phases used as long as the input voltage is greater than

the number of phases used times the output voltage. The

output ripple amplitude is also reduced by the number of

phasesused.Figure40graphicallyillustratestheprinciple.

The worst-case RMS ripple current for a single stage de-

sign peaks at an input voltage of twice the output voltage.

The worst case RMS ripple current for a 2-phase design

peaks at output voltages of 1/4 and 3/4 of the input volt-

age. When the RMS current is calculated, higher effective

duty factor results and the peak current levels are divided

as long as the current in each stage is balanced. Refer to

Application Note 19 at http://www.linear.com/designtools/

app_notes for a detailed description of how to calculate

RMS current for the single stage switching regulator. Fig-

ure 41 and Figure 42 illustrate how the input and output

currents are reduced by using an additional phase. For a

2-phase converter, the input current peaks drop in half and

the frequency is doubled. The input capacitor requirement

is then theoretically reduced by a factor of four.

LTC4449 Datasheet(PDF) 59 Page - Linear Technology

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