LTC4449 datasheet(45/108 Pages) LINER

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LTC3882-1

Rev A

For more information www.analog.com

APPLICATIONS INFORMATION

capacitance than is required to keep capacitance-based

droop under control.

The input capacitance voltage rating should be at least 1.4

times the maximum input voltage. Power loss due to ESR

occurs as I2R dissipation in the capacitor itself. The input

capacitor RMS current and its impact on any preceding

input network is reduced by PolyPhase architecture. It can

be shown that the worst case RMS current occurs when

only one controller is operating. The controller with the

highest (VOUT)(IOUT)productshouldbeusedtodetermine

the maximum RMS current requirement. Increasing the

output current drawn from the other out-of-phase control-

ler will decrease the input RMS ripple current from this

maximum value. Two channel out-of-phase operation

typically reduces the input capacitor RMS ripple current

by a factor of 30% to 70%.

In continuous inductor conduction mode, the source cur-

rent of the top power MOSFET is approximately a square

waveofdutycycleVOUT/VIN.ThemaximumRMScapacitor

current in this case is given by:

IRMS ≈IOUT(MAX)

VOUT VIN – VOUT

(

)

VIN

This formula has a maximum at VIN = 2VOUT, where

IRMS = IOUT/2

This simple worst-case condition is commonly used for

design because even significant deviations do not offer

much relief.

Notethatmanufacturerripplecurrentratingsforcapacitors

are often based on only 2000 hours of life. This makes

it advisable to further derate the capacitor or to choose

a capacitor rated at a higher temperature than required.

Several capacitors may also be paralleled to meet size or

height requirements in the design. Always consult the

manufacturer if there is any question.

Ceramic, tantalum, semiconductor electrolyte (OS-CON),

hybrid conductive polymer (SUNCON) and switcher-rated

electrolytic capacitors can be used as input capacitors, but

each has drawbacks. Ceramics have high voltage coeffi-

cients of capacitance and may have audible piezoelectric

effects; tantalums need to be surge-rated; OS-CONs suffer

fromhigherinductance,largercasesizeandlimitedsurface

mountapplicability;andelectrolyticcapacitorshavehigher

ESRandcandryout.SanyoOS-CONSVP(D)series,Sanyo

POSCAP TQC series, or Panasonic EE-FT series aluminum

electrolytic capacitors can be used in parallel with a couple

of high performance ceramic capacitors as an effective

means of achieving low ESR and high bulk capacitance.

InadditiontoPWMbulkinputcapacitance,asmall(0.01μF

to 1μF) bypass capacitor between the chip VINSNS pin

and ground, placed close to the LTC3882-1, is also sug-

gested. A small resistor placed between the bulk CIN and

the VINSNS pin provides further isolation between the two

channels. However, if the time constant of any such R-C

network on the VINSNS pin exceeds 30ns, dynamic line

transient response can be adversely affected.

COUT Selection

The selection of COUT is primarily determined by the ESR

requiredtominimizevoltagerippleandloadsteptransients.

The output ripple ∆VOUT is approximately bounded by:

ΔVOUT ≤ ΔIL ESR +

8 • f PWM •COUT

⎛

⎝⎜

⎞

⎠⎟

where ∆IL is the inductor ripple current.

ΔIL =

VOUT

L • f PWM

1–

VOUT

VIN

⎛

⎝⎜

⎞

⎠⎟

Since ∆IL increases with input voltage, the output ripple

voltage is highest at maximum input voltage. Typically

once the ESR requirement is satisfied, the capacitance is

adequate for filtering and has the necessary RMS current

rating.

Manufacturers such as Sanyo, Panasonic and Cornell Du-

bilier should be considered for high performance through-

hole capacitors. The OS-CON semiconductor electrolyte

capacitor available from Sanyo has a good (ESR)(size)

product. An additional ceramic capacitor in parallel with

polarized capacitors is recommended to offset the effect

of lead inductance.

In surface mount applications, multiple capacitors may

have to be paralleled to meet the ESR or transient current

LTC4449 Datasheet(PDF) 45 Page - Linear Technology

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