LTC4449 datasheet(48/108 Pages) LINER

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LTC3882-1

Rev A

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APPLICATIONS INFORMATION

noderiseandfalltimesshouldbeminimized.Thefollowing

PCB design priority list will help ensure proper topology.

1. Place a ground or DC voltage layer between a power

layer and a small-signal layer. Generally, power planes

should be placed on the top layer (4-layer PCB), or top

and bottom layer if more than 4 layers are used. Use

wide/short copper traces for power components and

avoid improper use of thermal relief around power

plane vias to minimize resistance and inductance.

2. Low ESR input capacitors should be placed as close

as possible to switching FET supply and ground con-

nections with the shortest copper traces possible. The

switching FETs must be on the same layer of copper

as the input capacitors with a common topside drain

connection at CIN. Do not attempt to split the input

decoupling for the two channels, as a large resonant

loop can result. Vias should not be used to make these

connections. Avoid blocking forced air flow to the

switching FETs with large size passive components.

3. If using a discrete FET driver, place that IC close to the

switching FET gate terminals, keeping the connecting

traces short to produce clean drive signals. This rule

also applies to driver IC supply and ground pins that

connect to the switching FET source pins. The driver

IC can be placed on the opposite side of the PCB from

the switching FETs.

4. Place the inductor input as close as possible to the

switchingFETs.Minimizethesurfaceareaoftheswitch

node. Make the trace width the minimum needed to

support the maximum output current. Avoid copper

fillsorpours.Avoidrunningtheconnectiononmultiple

copper layers in parallel. Minimize capacitance from

the switch node to any other trace or plane.

5. Place the output current sense resistor (if used) im-

mediately adjacent to the inductor output. PCB traces

for remote voltage and current sense should be run

together back to the LTC3882-1 in pairs with the small-

est spacing possible on any given layer on which they

are routed. Avoid high frequency switching signals

and ideally shield with ground planes. Locate any filter

component on these traces next to the LTC3882-1,

and not at the Kelvin sense location. However, if DCR

sensing is used, place the top resistor (R1, Figure 25)

close to the switch node.

6. Place low ESR output capacitors adjacent to the sense

resistor output and ground. Output capacitor ground

connections must feed into the same copper that con-

nects to the input capacitor ground before connecting

back to system ground.

7. Connection of switching ground to system ground,

small-signalanaloggroundoranyinternalgroundplane

should be single-point. If the system has an internal

system ground plane, a good way to do this is to cluster

viasintoasinglestarpointtomaketheconnection.This

cluster should be located directly beneath the IC GND

paddle, which serves as both analog signal ground and

the negative sense for VOUT1. A useful CAD technique

is to make separate ground nets and use a 0Ω resistor

to connect them to system ground.

8. Place all small-signal components away from high

frequency switching nodes. Place decoupling capaci-

tors for the LTC3882-1 immediately adjacent to the IC.

9. A good rule of thumb for via count in a given high cur-

rent path is to use 0.5A per via. Be consistent when

applying this rule.

10. Copper fills or pours are good for all power connec-

tions except as noted above in rule 3. Copper planes

on multiple layers can also be used in parallel. This

helps with thermal management and lowers trace

inductance, which further improves EMI performance.

Output Current Sensing

The ISENSE+ and ISENSE– pins are high impedance inputs to

internalcurrentcomparators,thecurrent-sharingloopand

telemetry ADC. The common mode range of the current

senseinputsisapproximately0Vto5.5V.Continuouslinear

operation is provided throughout this range. Maximum

differentialcurrentsenseinput(ISENSE+–ISENSE–)is70mV,

including any variation over temperature. These inputs

must be properly connected in the application at all times.

TomaximizeefficiencyatfullloadtheLTC3882-1isdesigned

to sense current through the inductor’s DCR, as shown in

Figure 25. The DCR of the inductor represents the small

amount of DC winding resistance of the copper, which

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