LTC4449 datasheet(24/108 Pages) LINER

24 / 108 page

LTC3882-1

Rev A

For more information www.analog.com

OPERATION

The PHAS_CFG pin settings are described in Table 10.

This pin selects the phase relationships between the two

channels and the selected clock source.

Internal EEPROM with CRC and ECC

The LTC3882-1 contains internal EEPROM with Error

Correcting Coding (ECC) to store user configuration set-

tings and fault log information. EEPROM endurance and

retention for user space and fault log pages are specified

in the Absolute Maximum Ratings and Electrical Charac-

teristics table.

TheintegrityoftheentireonboardEEPROMischeckedwith

a CRC calculation each time its data is to be read, such as

after a power-on reset or execution of a RESTORE_USER_

ALL command. If a CRC error occurs, the CML bit is set

in the STATUS_BYTE and STATUS_WORD commands, the

EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC

command is set, and the ALERT and RUN pins pulled

low (PWM channels off). At that point the device will only

respond at special address 0x7C, which is activated only

after an invalid CRC has been detected. The chip will also

respond at the global addresses 0x5A and 0x5B, but use

of these addresses when attempting to recover from a

CRC issue is not recommended. All power supply rails

associated with either PWM channel of a device reporting

an invalid CRC should remain disabled until the issue is

resolved.

LTC recommends that the EEPROM not be written when

die temperature is greater than 85°C. If internal die tem-

perature exceeds 130°C, all EEPROM operations except

RESTORE_USER_ALL and MFR_RESET are disabled. Full

EEPROM operation is not re-enabled until die temperature

falls below 125°C. Refer to the Applications Information

section for equations to predict retention degradation due

to elevated operating temperatures.

See the Applications Information section or contact the

factoryfordetailsonefficientin-systemEEPROMprogram-

ming, including bulk EEPROM programming, which the

LTC3882-1 also supports.

Fault Detection

A variety of fault and warning detection, reporting and

handling mechanisms are provided by the LTC3882-1.

Fault or warning detection capabilities include:

• Input Under/Overvoltage

• Output Under/Overvoltage

• Output Overcurrent (Peak and Average)

• Internal and External Overtemperature and External

Undertemperature

• CML Fault (Communication, Memory, or Logic)

• External Fault Detection via Bidirectional FAULT Pins

Reporting is covered in following sections on status com-

mands (registers) and ALERT pin function. Fault handling

mechanisms include hardwired, low-level PWM safety

responses that always occur, and higher-level program-

mable event management. Both types are covered in the

following sections.

Input Supply Faults

Input undervoltage and overvoltage limits are determined

from multiplexed monitor ADC conversions. Therefore the

input UV/OV response is naturally deglitched by the 90ms

typical conversion cycle of the ADC. There is no hardwired

low-level PWM response for any input supply fault.

Hardwired PWM Response to VOUT Faults

VOUT undervoltage (UV) and overvoltage (OV) faults are

detected by supervisor comparators. The OV and UV fault

limits can be set in three ways:

• As a Percentage of VOUT if Using the Resistor Configu-

ration Pins

• From Stored EEPROM Values

• By PMBus Command

Theoutputovervoltagecomparatorguardsagainsttransient

overshootsaswellaslongtermovervoltagesattheoutput.

When an output OV fault is detected the top MOSFET for

that channel is commanded off and the bottom MOSFET is

commanded on until the overvoltage condition is cleared

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