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LTC4449 Datasheet(PDF) 33 Page - Linear Technology |
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LTC4449 Datasheet(HTML) 33 Page - Linear Technology |
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33 / 108 page ![]() LTC3882-1 33 Rev A For more information www.analog.com OPERATION Global addressing provides a means for the bus master to communicate with all LTC3882-1 devices on the bus simultaneously. The LTC3882-1 global addresses of 0x5A and 0x5B cannot be changed or disabled. Commands sent to address 0x5A are applied to both channels, as if the PAGE command were set to 0xFF. Global address 0x5B is paged, allowing channel-specific control of all LTC3882-1 devices on the bus. Other LTC device types may respond at one or both of these global addresses. Reading from global addresses is strongly discouraged. Rail addressing provides a means for the bus master to simultaneously communicate with all channels connected together to produce a single output voltage (PolyPhase). While similar to global addressing, the rail address can be dynamically assigned with the paged MFR_RAIL_AD- DRESS command, allowing for any logical grouping of channelsthatmightberequiredforreliablesystemcontrol. Rail addresses should be unique for each single-phase or PolyPhase rail. Different voltage rails should not attempt to share a rail address. Reading from rail addresses is also strongly discouraged. Device addressing is the most common means used by a bus master to communicate with an LTC3882-1. The value of the device address is set by the combination of ASEL pin programming and the MFR_ADDRESS command. Refer to the previous section on Resistor Configuration Pins for details. Individual channel addressing allows the bus master to communicate directly with a specific LTC3882-1 PWM channel without first using a PAGE command. Refer to the PAGE_PLUS commands for additional details. Use of any of the four types of addressing requires careful planning to avoid address-related bus conflicts. Commu- nication to LTC3882-1 devices at global and rail addresses should be limited to command write operations. Figure 4. Quick Command Protocol Figure 5. Send Byte Protocol Figure 6. Send Byte Protocol with PEC Figure 3. PMBus Packet Protocol Diagram Element Key 38821 F03 S START CONDITION Sr REPEATED START CONDITION Rd READ (BIT VALUE OF 1) Wr WRITE (BIT VALUE OF 0) A ACKNOWLEDGE (BIT SHOULD BE 0), OR NA NOT ACKNOWLEDGE (BIT SHOULD BE 1) P STOP CONDITION PEC PACKET ERROR CODE MASTER TO SLAVE SLAVE TO MASTER CONTINUATION OF PROTOCOL ... SLAVE ADDRESS Rd/Wr A P 38821 F04 S 7 1 1 1 1 SLAVE ADDRESS COMMAND CODE Wr A A P 38821 F05 S 7 8 1 1 1 1 1 SLAVE ADDRESS COMMAND CODE PEC Wr A A A P 38821 F06 S 7 8 8 1 1 1 1 1 1 |
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