LTC4449 datasheet(25/108 Pages) LINER

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LTC3882-1

Rev A

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OPERATION

or for PWM control protocol 0, reverse overcurrent is

detected. See IOUT faults below.

UV faults and warnings are masked if the channel has

been commanded off or until all of the following criteria

are achieved.

• TON_DELAY Has Expired

• TON_RISE Ramp Has Completed

• TON_MAX_FAULT_LIMIT Has Been Reached

• IOUT_OC_FAULT_LIMIT Has Not Been Reached

• TOFF_FALL Is Not in Progress

Output UV warnings are determined from multiplexed

monitor ADC conversions. The LTC3882-1 has no hard-

wired PWM response for output UV faults or warnings.

Power Good Indication (Master)

An LTC3882-1 master phase indicates Power Good on its

PGOOD pin and in PMBus commands STATUS_WORD

(paged) and MFR_PADS_LTC3882-1 based on pro-

grammed UV and OV fault limits. Power Good is indicated

on a master phase as long as it is enabled to run and VOUT

is between the UV and OV fault limits. If a master chan-

nel is off for any reason, its PGOOD pin is driven low and

Power Not Good is indicated in the status commands.

Power Good Indication (Slave)

As long as they are enabled, slave phases indicate Power

Good on PGOOD and in PMBus status commands, unless

a master error amplifier (EA) fault is detected. An EA fault

indicatesthebussedCOMPvoltageappearstobetoohigh.

When a slave detects an EA fault, its output is immedi-

dately disabled and OV is indicated (see Figure 2). Any

valid higher-level OV fault response and propagation may

be set for a slave channel to handle a detected EA fault. If

the OV fault response is set to ignore, the slave output is

re-enabled when the EA/COMP condition clears.

AslaveindicatesPowerNotGoodwithPMBusstatuscom-

mands during an EA fault, but its PGOOD pin remains high

impedance. If a slave phase is off for any other reason, its

PGOOD pin is also driven low.

Hardwired PWM Response to IOUT Faults

The LTC3882-1 measures average IOUT from the voltage

acrosstheISENSEpins,takingintoaccountthesenseresistor

or DCR value and its associated temperature coefficient.

BothareprovidedbyPMBuscommandorEEPROMvalues.

An output overcurrent (OC) fault condition is detected by

a supervisor comparator for each PWM output when the

sensed instantaneous current for that channel reaches

its maximum allowed value. Refer to the IOUT_OC_

FAULT_LIMIT PMBus command for details. When an OC

fault is detected the controller immediately disables the

top FET, and the bottom FET is normally commanded on

for the remainder of that PWM cycle.

If programmed to operate in CCM, the LTC3882-1 also

uses the negative of IOUT_OC_FAULT_LIMIT to detect

a reverse overcurrent (ROC) fault. When an ROC fault

occurs the controller immediately disables both top and

bottom FETs, unless PWM output protocol 1 is selected

with MFR_PWM_MODE_LTC3882-1.

OC and ROC faults are both handled according to the

IOUT_OC_FAULT_RESPONSE for that channel. Either

hardware response can result in current-limited operation

usingpulsetruncationorskipping.BecausetheLTC3882-1

uses leading edge modulation, this will cause a shift in

average phase toward 0° on the faulted channel and an

increase in input ripple current

Output OC warnings are determined from multiplexed

monitorADCconversions.TheLTC3882-1hasnohardwired

PWM response if an output OC warning occurs.

Hardwired PWM Response to Temperature Faults

An internal temperature sensor measured by the moni-

tor ADC protects against EEPROM and other IC damage.

When die temperature rises above 130°C, the LTC3882-1

will NACK any EEPROM-related command except RE-

STORE_USER_ALL and MFR_RESET and issue a CML

faultforInvalid/UnsupportedCommand.NormalEEPROM

access is re-enabled when die temperature drops below

125°C.Above160°C,thepartshutsdownallPWMoutputs

until die temperature is below 150°C. Internal temperature

fault limits cannot be adjusted. Writing to the EEPROM

above a die temperature of 85°C is strongly discouraged.

LTC4449 Datasheet(PDF) 25 Page - Linear Technology

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