LTC4449 datasheet(19/108 Pages) LINER

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LTC3882-1

Rev A

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VC discriminates its positive input against an internally

generated PWM voltage ramp. The positive input is a com-

positecontrolbasedonCOMPvoltagewithlinefeedforward

compensation, and current sharing if the channel controls

a slave phase. When the ramp falls below this voltage the

comparator trips and sets the PWM latch.

If load current increases, VSENSE+ and FB will droop

slightly with respect to the 12-bit DAC output. This causes

the COMP voltage to increase until the average inductor

current matches the new load current and the desired

output voltage is restored. Programmable comparators

ILIM and IREV monitor peak instantaneous forward and

reverse inductor current for pulse-by-pulse protection.

The top power MOSFET is immediately commanded off if

the programmed positive limit is reached, and the bottom

MOSFET is immediately commanded off if the negative

limit is reached. Repeated peak overcurrent events cause

an overcurrent fault to be set.

When the top MOSFET is commanded off, the bottom

MOSFET is normally commanded on. In continuous con-

duction mode (CCM) the bottom MOSFET stays on until

comparator VC turns the top MOSFET back on. Otherwise

in discontinuous conduction mode (DCM, also known as

diode emulation) the bottom MOSFET is commanded off

if the IREV comparator detects that the inductor current

has decayed to approximately 0A. In any case the next

PWM cycle starts when the clock for that channel again

clears the RS latch.

Power-Up and Initialization

The LTC3882-1 is designed to provide stand-alone supply

sequencingwithcontrolledturn-onandturn-offfunctions.

It operates from a single IC input supply of 3V to 13.2V

while two on-chip linear regulators generate internal

2.5V and 3.3V. If VCC is below 4.5V, the VCC and VDD33

pins must be shorted together and limited to a maximum

operating voltage of 3.6V. Controller configuration is

reset by the internal UVLO threshold, where VDD33 must

be at or above 3V and the internal 2.5V supply must be

within about 20% of its regulated value. At that point the

internal microcontroller begins initialization. A PMBus

RESTORE_USER_ALL or MFR_RESET command forces

this same initialization.

The LTC3882-1 features an internal RAM built-in self-test

(BIST) that runs during initialization. Should RAM BIST

fail, the following steps are taken.

• Devicerespondsonlyatdeviceaddress0x7Candglobal

addresses 0x5A and 0x5B

• A persistent Memory Fault Detected is indicated by

STATUS_CML

• Internal EEPROM is not accessed

• RUN

n and SHARE_CLK are driven low continuously

Normal operation can be restored if the RAM BIST sub-

sequently passes, for instance as the result of another

MFR_RESET command issued to address 0x7C.

During initialization all PWM outputs are disabled. The

RUNn pins and SHARE_CLK are held low and FAULTn

pins are high impedance. External configuration resistors

are identified and the contents of the onboard EEPROM

are read into the controller command memory space. The

LTC3882-1 can determine key operating parameters from

external configuration resistors according to application

Table 8 through Table 11. See the following Resistor

Configuration Pins section for more detail. The resistor

configuration pins only determine some of the preset

values of the controller. The remaining values, retrieved

from internal EEPROM, are programmed at the factory or

with PMBus commands.

Iftheconfigurationresistorpinsareallopen,theLTC3882-1

will use only EEPROM contents to determine all operating

parameters.IfIgnoreResistorConfigurationPinsisset(bit

6 of MFR_CONFIG_ALL_LTC3882-1), the LTC3882-1 will

use only its EEPROM contents to determine all operating

parameters except device address. Unless both ASEL pins

are completely open, the LTC3882-1 will always determine

some portion of its device address from the resistors on

these pins. See Serial Bus Addressing later in this section.

The internal microcontroller typically requires 35ms to

complete initialization from VDD33 ≥ 3V. At that point, an

internalcomparatormonitorsVINSNS,whichmustexceed

the VIN_ON threshold before output power sequencing

can begin (SHARE_CLK released, ready for TON_DELAY).

Accuratereadbacktelemetrycanthenrequireanadditional

90ms for initial round-robin A/D conversions.

OPERATION

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