LTC4449 datasheet(14/108 Pages) LINER

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LTC3882-1

Rev A

For more information www.analog.com

PIN FUNCTIONS

PHAS_CFG (Pin 21): Phase Configuration Pin. Connect

an optional 1% resistor divider between VDD25 and GND

to this pin to configure the phase of each PWM channel

relative to SYNC. Refer to the Applications Information

section for more detail.

VDD25 (Pin 22): Internal 2.5V Regulator Output. Bypass

this pin to GND with a low ESR 1µF capacitor. Do not load

this pin with external current beyond that required for local

LTC3882-1 configuration pins, if any.

SHARE_CLK (Pin 23): Share Clock Open-Drain Output

(bussed). Share Clock, nominally 100kHz, is used to

sequence multiple rails in a power system utilizing more

than one LTC PSM controller. A pull-up resistor is required

in the application. Minimize the capacitance on this line to

ensure the time constant is fast enough for the application.

Operating voltage range is GND to VDD33.

VDD33(Pin24):Internal3.3VRegulatorOutput.Bypassthis

pin to GND with a low ESR 2.2µF capacitor. The LTC3882-1

may also be powered from an external 3.3V rail attached

to this pin, if also shorted to VCC. Do not overload this pin

with external system current. Local pull-up resistors for

the LTC3882-1 itself may be powered from VDD33. Refer

to the Applications Information section for more detail.

VCC (Pin 25): 3.3V Regulator Input. Bypass this pin to

GND with a capacitor (0.1µF to 1µF ceramic) in close

proximity to the IC.

VSENSE0–/VSENSE1– (Pin 35/Pin 34): Negative Output

Voltage Sense Inputs. These pins must still be properly

connected on slave channels for accurate output current

telemetry.

VSENSE0+/VSENSE1+(Pin36/Pin33):PositiveOutputVoltage

Sense Inputs. These pins must still be properly connected

on slave channels for accurate output current telemetry.

ISENSE0–/ISENSE1– (Pin 37/Pin 32): Current Sense Ampli-

fier Inputs. The (–) inputs to the amplifiers are normally

connected to the low side of a DCR sensing network or

output current sense resistor for each phase.

ISENSE0+/ISENSE1+ (Pin 38/Pin 31): Current Sense Ampli-

fier Inputs. The (+) inputs are normally connected to the

high side of an output current sense resistor or the R-C

midpoint of a parallel DCR sense circuit.

IAVG0/IAVG1(Pin39/Pin30):AverageCurrentControlPins.

A capacitor connected between these pins and IAVG_GND

stores a voltage proportional to the average output current

of the master channel. PolyPhase control is then imple-

mented in part by connecting all slave IAVG pins together

to the master IAVG output. This pin should be left open

on channels that control single-phase outputs. Operating

voltage range is GND to 2.1V.

FB0/FB1 (Pin 40/Pin 29): Error Amplifier Inverting Inputs.

These pins provide an internally scaled version of the

output voltage for use in loop compensation. Refer to the

Applications Information section for additional details on

compensatingtheoutputvoltagecontrolloopwithexternal

components.

GND (Exposed Pad Pin 41): Ground. All small-signal and

compensation components should connect to this pad.

TheexposedpadmustbesolderedtoasuitablePCBcopper

ground plane for proper electrical operation and to obtain

the specified package thermal resistance.

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