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LTC3882-1

Rev A

For more information www.analog.com

APPLICATIONS INFORMATION

3. Set MFR_VOUT_AVP to a percentage that produces the

desired output excursion as a function of current.

For example, if the goal is to allow a 2.5% output change

on a 3.3V 6-phase supply rated at 120A during an output

load step from 20% to 80%, the following parameters

should be programmed.

Firstsetanoutputcurrentwarninglevelforthemaster(one

of six phases) just slightly higher than the rated full load

to avoid spurious warnings. Typically this same setting

would also be applied to the five slave phases.

IOUT_OC_WARN_LIMIT = 1.1 • 120A/6 = 22A

The open circuit output voltage calculation for the master

phase must reflect that the AVP specification in this case

only covers an output load swing of 60%.

VOUT_COMMAND = 3.3V(1 + 0.5 • 0.025/0.6)

= 3.3687V

The AVP calculation must then account for the fact that

IOUT_OC_WARN_LEVEL is set higher than the 100%

load point.

MFR_VOUT_AVP =

100% •1.1• 2 • 3.3687 – 3.3

(

)

3.3687

= 4.487%

With the output voltage at 3.3V at 50% load these set-

tings will move VOUT from approximately 3.34V to about

3.26V when the output load of the rail moves from 24A

to 96A. Note that VOUT will drop to 3.23V at full load in

this design example.

Digital output servo mode is automatically disabled if

AVP is enabled on a master phase. AVP is active during

all output ramping when enabled (e.g., a TON_RISE se-

quence). AVP is disabled on master phases by program-

ming MFR_VOUT_AVP to 0.0% (factory default). AVP is

automatically disabled on phases configured as slaves

(FB tied to VDD33).

Because of related ISENSE input offsets, increased output

voltage error can occur at all operating currents when AVP

is engaged. To minimize this error a calibration offset can

be added to the master phase VOUT_COMMAND value

based on the READ_VOUT value obtained when operat-

ing at a known output current of at least 20% of full load

(READ_IOUT). The necessary correction, which will typi-

cally be less than several percent of the no load output

voltage, is calculated as:

VOS = VOUT_COMMAND

• 1–

MFR_VOUT_AVP •READ_IOUT

100 •IOUT_OC_WARN_LIMIT

⎛

⎝⎜

⎞

⎠⎟

– READ_VOUT

PWM Frequency Synchronization

The LTC3882-1 incorporates an internal phase-locked

loop (PLL) which enables synchronization of both PWM

channels (falling edge PWM) to an external CMOS clock

from 250kHz to 1.25MHz. The PLL is locked to the falling

edge of the SYNC pin clock signal. This PLL also generates

very accurate channel phase relationships which can be

selected with the MFR_PWM_CONFIG_LTC3882-1 com-

mand. For PolyPhase applications, all phases should be

spaced evenly in the phase diagram for best results. For

instance, a 4-phase system should use a separation of

90° between channels.

The PLL has a lock detection circuit. If the PLL should lose

lockduringoperation,bit4oftheSTATUS_MFR_SPECIFIC

command is asserted and the ALERT pin is pulled low,

unless masked. The fault can be cleared by writing a 1 to

STATUS_MFR_SPECIFIC bit 4. A spurious ALERT for an

unlocked PLL may occur at start-up or during a reset if

this fault is not masked.

Neither PWM channel will transition from off to the RUN

state until PLL lock is indicated. When transitioning a

channel from off to RUN, bit 4 of STATUS_MFR_SPECIFIC

will be set if the PWM ramp generator for that channel

is not also locked to the desired PLL output frequency.

If the SYNC pin is not externally clocked in the application,

the PWMs will operate at the frequency specified by a non-

zero FREQUENCY_SWITCH command. If that command

is set to 0x0000 (external clock only) in EEPROM or with

RCONFIG (FREQ_CFG pin grounded), then at power-up,

or MFR_RESET, or RESTORE_USER_ALL, the PWM will

not start without an external clock input. If the external

clock is lost while programmed for external clock only, or

if the PWM is simply switched to this setting under power

with no external clock present, the PLL will start/run at

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