LTM4677 datasheet(44/116 Pages) AD

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LTC3883/LTC3883-1

Rev. F

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APPLICATIONS INFORMATION

TheoptionalSchottkydiodesconductduringthedeadtime

betweentheconductionofthetwopowerMOSFETs.These

preventthebodydiodesofthebottomMOSFETsfromturn-

ing on, storing charge during the dead time and requiring

a reverse recovery period that could cost as much as 3%

in efficiency at high VIN. A 1A to 3A Schottky is generally

a good compromise for both regions of operation due to

the relatively small average current. Larger diodes result

in additional transition losses due to their larger junction

capacitance.

VARIABLE DELAY TIME, SOFT-START AND OUTPUT

VOLTAGE RAMPING

The LTC3883 must enter the run state prior to soft-start.

The RUN pin is released after the part initializes and VIN is

greater than the VIN_ON threshold. If multiple LTC3883s

are used in an application, they should be configured to

share the same RUN pins. They all hold their respective

RUN pins low until all devices initialize and VIN exceeds

the VIN_ON threshold for all devices. The SHARE_CLK

pin assures all the devices connected to the signal use

the same time base.

After the RUN pin releases, the controller waits for the

user-specified turn-on delay (TON_DELAY) prior to ini-

tiating an output voltage ramp. Multiple LTC3883s and

other ADI parts can be configured to start with variable

delay times. To work correctly, all devices use the same

timing clock (SHARE_CLK) and all devices must share

the RUN pin. This allows the relative delay of all parts to

be synchronized. The actual variation in the delay will be

dependent on the highest clock rate of the devices con-

nected to the SHARE_CLK pin (all Linear Technology ICs

are configured to allow the fastest SHARE_CLK signal to

control the timing of all devices). The SHARE_CLK signal

can be ±10% in frequency, thus the actual time delays will

have proportional variance.

Soft-start is performed by actively regulating the load volt-

age while digitally ramping the target voltage from 0.0V

to the commanded voltage set point. The rise time of the

voltage ramp can be programmed using the TON_RISE

command to minimize inrush currents associated with the

start-up voltage ramp. The soft-start feature is disabled

by setting TON_RISE to any value less than 0.250ms.

The LTC3883 will perform the necessary math internally

to assure the voltage ramp is controlled to the desired

slope. However, the voltage slope can not be any faster

thanthefundamentallimitsofthepowerstage.Theshorter

TON_RISEtimeisset,themorejaggedtheTON_RISEramp

will appear. The number of steps in the ramp is equal to

TON_RISE/0.1ms.

The LTC3883 PWM will always use discontinuous mode

during the TON_RISE operation. In discontinuous mode,

the bottom gate is turned off as soon as reverse current

is detected in the inductor. This will allow the regulator to

start up into a pre-biased load.

There is no tracking feature in the LTC3883; how-

ever, two outputs can be given the same TON_RISE and

TON_DELAY times to effectively ramp up at the same

time. If the RUN pin is released at the same time and both

LTC3883s use the same time base, the outputs will track

very closely. If the circuit is in a PolyPhase configuration,

all timing parameters must be the same.

Thedescribedmethodofstart-upsequencingistimebased.

For concatenated events it is possible to control the RUN

pinbasedontheGPIOpinofadifferentcontroller.TheGPIO

pincanbeconfiguredtoreleasewhentheoutputvoltageof

theconverterisgreaterthantheVOUT_UV_FAULT_LIMIT.

It is recommended to use the deglitched VOUT UV fault

limit because there is little appreciable time delay between

the converter crossing the UV threshold and the GPIO pin

releasing. The deglitched output can be enabled by set-

ting the MFR_GPIO_PROPAGATE_VOUT_UVUF bit in the

MFR_GPIO_PROPAGATE_LTC3883 command. (Refer to

the MFR section of the PMBus commands in this docu-

ment). The deglitched signal may have some glitching

as the VOUT signal transitions through the comparator

threshold. A small internal digital filter of 70µs has been

added to minimize this problem. To minimize the risk of

GPIO pin glitching, make the TON_RISE times less than

100ms.IfunwantedtransitionsstilloccuronGPIO,placea

capacitor to ground on the GPIO pin to filter the waveform.

The RC time-constant of the filter should be set sufficiently

fast to assure no appreciable delay is incurred. A value

of 300µs to 500µs will provide some additional filtering

without significantly delaying the trigger event.

LTM4677 Datasheet(PDF) 44 Page - Analog Devices

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