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LTM4677 Datasheet(PDF) 71 Page - Analog Devices |
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LTM4677 Datasheet(HTML) 71 Page - Analog Devices |
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71 / 116 page ![]() LTC3883/LTC3883-1 71 Rev. F For more information www.analog.com Bit[3] Setting this bit to a 1 starts the patent pending inductor DCR auto calibration to determine the DCR of the in- ductor. This will update the value of IOUT_CAL_GAIN using the READ_IIN, READ_IOUT, and DUTY_CYCLE values. IOUT_CAL_GAIN is adjusted so that READ_IOUT • DUTY_CYCLE = READ_IIN. The auto calibration procedure will only complete successfully if the following conditions are met. 1) The PWM is enabled 2) DUTY_CYCLE is at least 3% 3) READ_IIN is at least 10mA 4) The calibrated IOUT_CAL_GAIN is within ±30% of the uncalibrated IOUT_CAL_GAIN If any of the above conditions are not met, bit 0 of the STATUS_CML command will be set, and the value of IOUT_ CAL_GAIN will not be changed. Bit[3] must then be reset to a 0 by the user. A STORE_USER_ALL command must be issued to store the updated IOUT_CAL_GAIN value into NVM. Bit[1:0] determine the PWM mode of operation. This command has one data byte. MFR_PWM_CONFIG_LTC3883 The MFR_PWM_CONFIG_LTC3883 command sets the switching frequency and phase offset with respect to the fall- ing edge of the SYNC signal. The part must be in the OFF state to process this command. The RUN pin must be low or the part must be commanded off. If the part is in the RUN state and this command is written, the command will be ignored and a BUSY fault will be asserted. Bit 6 of this command affects the loop gain of the PWM output which may require modifications to the external compensation network. BIT MEANING 7 Reserved, set to 0. 6 If VOUT RANGE = 1, the maximum output voltage is 2.75V. If RANGE = 0, the maximum output voltage is 5.5V. 5 Reserved 4 Share Clock Enable : If this bit is 1, the SHARE_CLK pin will not be released until VIN > VIN_ON. The SHARE_CLK pin will be pulled low when VIN < VIN_OFF. If this bit is 0, the SHARE_CLK pin will not be pulled low when VIN < VIN_OFF except for the initial application of VIN. 3 Reserved, set to 0 BIT [2:0] Phase Offset 000b 0 001b 90 010b 180 011b 270 100b 60 101b 120 110b 240 111b 300 This command has one data byte. PMBus COMMAND DETAILS |
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