LTM4677 datasheet(26/116 Pages) AD

26 / 116 page

LTC3883/LTC3883-1

Rev. F

For more information www.analog.com

OPERATION

fault, one or more of the LTC3883s is configured to pull

the bussed GPIO pin low. The other LTC3883s are then

configured to shut down when the GPIO pin bus is pulled

low. For autonomous group retry, the faulted LTC3883

is configured to let go of the GPIO pin bus after a retry

interval, assuming the original fault has cleared. All the

LTC3883s in the group then begin a soft-start sequence.

If the fault response is LATCH_OFF, the GPIO pin remains

asserted low until either the RUN pin is toggled OFF/ON or

the part is commanded OFF/ON. The toggling of the RUN

either by the pin or OFF/ON command will clear faults as-

sociated with the LTC3883. If it is desired to have all faults

cleared when either RUN pin is toggled, set bit 0 of MFR_

CONFIG_ALL_LTC3883 to a 1.

The status of all faults and warnings is summarized in the

STATUS_WORD and STATUS_BYTE commands.

Additional fault detection and handling capabilities are:

Internal Memory with CRC and ECC

The LTC3883 contains internal EEPROM with Error Cor-

rection Coding (ECC) to store user configuration settings

and fault log information. EEPROM endurance and reten-

tion are specified in the Absolute Maximum Ratings and

Electrical Characteristics table.

The integrity of the NVM memory is checked with a

CRC calculation each time its data is to be read, such

as after a power-on reset. A CRC failure will prevent the

controller from leaving the inactive state. If a CRC failure

occurs, the CML bit is set in the STATUS_BYTE and

STATUS_WORD commands, the appropriate bit is set in

theSTATUS_MFR_SPECIFICcommand,andtheALERTand

RUN pins will be pulled low. At that point the device will

respond at special address 0x7C, which is only activated

after an invalid CRC has been detected. The chip will also

respond to global addresses 0x5A and 0x5B, but all ADI

PSM chips will respond to these addresses so users must

be careful when using global addresses. NVM repair can

be attempted by writing the desired configuration to the

controller and executing a STORE_USER_ALL command

followed by a CLEAR_FAULTS command. Contact the

factory if EEPROM repair is unsuccessful.

See the Applications Information section or contact the

factory for details on efficient in-system EEPROM pro-

gramming, including bulk EEPROM programming, which

the LTC3883 also supports.

SERIAL INTERFACE

The LTC3883 serial interface is a PMBus compliant slave

device and can operate at any frequency between 10kHz

and 400kHz. The address is configurable using either the

NVMoranexternalresistordivider.InadditiontheLTC3883

always responds to the global broadcast address of 0x5A

(7 bit) or 0x5B (7 bit).

Theserialinterfacesupportsthefollowingprotocolsdefined

in the PMBus specifications: 1) send command, 2) write

byte, 3) write word, 4) group, 5) read byte, 6) read word

and 7) read block. All read operations will return a valid

PECifthePMBusmasterrequestsit.IfthePEC_REQUIRED

bit is set in the MFR_CONFIG_ALL_LTC3883 command,

the PMBus write operations will not be acted upon until

a valid PEC has been received by the LTC3883.

Communication Failure

PEC write errors (if PEC_REQUIRED is active), attempts

to access unsupported commands, or writing invalid data

to supported commands will result in a CML fault. The

CML bit is set in the STATUS_BYTE and STATUS_WORD

commands, the appropriate bit is set in the STATUS_CML

command, and the ALERT pin is pulled low.

DEVICE ADDRESSING

TheLTC3883offersfourdifferenttypesofaddressingover

the PMBus interface, specifically: 1) global, 2) device, 3)

rail addressing and 4) alert response address (ARA).

Global addressing provides a means of the PMBus master

to address all LTC3883 devices on the bus. The LTC3883

global address is fixed 0x5A (7 bit) or 0xB4 (8 bit) and can-

not be disabled.

LTM4677 Datasheet(PDF) 26 Page - Analog Devices

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