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LTM4677 Datasheet(PDF) 16 Page - Analog Devices

Part # LTM4677
Description  Single Phase Step-Down DC/DC Controller with Digital Power System Management
PDF  116 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTM4677 Datasheet(HTML) 16 Page - Analog Devices

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LTC3883/LTC3883-1
16
Rev. F
For more information www.analog.com
BLOCK DIAGRAM
16-BIT
ADC
PWM1
+
–
–+
–
–+
+
+
+
––
PWM0
–+
–
+
–
+
8:1
MUX
TMUX
2µA
ILIM DAC
(3 BITS)
OV
8-BIT
OV
DAC
8-BIT
UV
DAC
12-BIT
SET POINT
DAC
UV
EA
+
0.56V
1.22V
BURST
ITH
RC
CC1
GND
30µA
–
+
AO
R
R
9R
2R
GND
PWM
CLOCK
VOUT_CFG
R
VSENSE+
TSNS
VSENSE–
R
SWITCH
LOGIC
AND
ANTI-
SHOOT-
THROUGH
OV
RUN
SS
UVLO
REV
UV
ON
FCNT
31
30
32
15
VTRIM_CFG
17
FREQ_CFG
14
ASEL
3883 F01
13
9
11
PGND
CINTVCC
25
BG
DB
M1
INTVCC/EXTVCC
VDD33
26
ISENSE–
4
ISENSE+
3
SW
22
TG
CB
23
BOOST
24
VDD33
21
VIN
CVIN
28
1
INTVCC/EXTVCC (LTC3883-1)
27
M2
COUT
VOUT
+
3.3V
SUBREG
2.5V
SUBREG
5V REG
–
+
1
71.1k
ACTIVE
CLAMP
UVLO
INTVCC
SLOPE
COMPENSATION
SLAVE
VDD33
MISO
MOSI
CLK
MASTER
RAM
SYNC
RUN
10
PGOOD
GPIO
EEPROM
MAIN
CONTROL
PROGRAM
ROM
VDD33
COMPARE
ILIM RANGE SELECT
HI: 1:1
LO: 1:1.5
3k
38R
IIN
R
ICMP
IREV
29
33
1Ω
+
–
S
REF
VSTBY
GND
Q
PWM_CLOCK
VIN_SNS
RIINSNS
RVIN
VIN
CIN
2
IIN_SNS
R
8-BIT
VIN_ON
THRESHOLD DAC
PHASE DET
VCO
PHASE SELECTOR
CLOCK DIVIDER
SINC3
UVLO
OSC
(32MHz)
CONFIG
DETECT
CHANNEL
TIMING
MANAGEMENT
8
7
6
19
WP
SHARE_CLK
SCL
SDA
ALERT
PMBus
INTERFACE
(400kHz
COMPATIBLE)
20
SYNC
GND
M2
GND
VDD33
5
VDD25
18
VDD25
LTC3883
ONLY
19.5R
R
+
Figure 1. Block Diagram



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