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LTM4677 Datasheet(PDF) 8 Page - Analog Devices |
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LTM4677 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 116 page  LTC3883/LTC3883-1 8 Rev. F For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 12V, VRUN = 3.3V, fSYNC = 500kHz (externally driven) unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SYNC- SYNC to Channel Phase Relationship Based on the Falling Edge of Sync and Rising Edge of TG MFR_PWM_CONFIG_LTC3883[2:0] = 0 MFR_PWM_CONFIG_LTC3883[2:0] = 1 MFR_PWM_CONFIG_LTC3883[2:0] = 2 MFR_PWM_CONFIG_LTC3883[2:0] = 3 MFR_PWM_CONFIG_LTC3883[2:0] = 4 MFR_PWM_CONFIG_LTC3883[2:0] = 5 MFR_PWM_CONFIG_LTC3883[2:0] = 6 MFR_PWM_CONFIG_LTC3883[2:0] = 7 0 90 180 270 60 120 240 300 Deg Deg Deg Deg Deg Deg Deg Deg EEPROM Characteristics Endurance (Note 13) 0°C < TJ < 85°C During EEPROM Write Operations l 10,000 Cycles Retention (Note 13) TJ < 125°C l 10 Years Mass_Write Mass Write Operation Time STORE_USER_ALL, 0°C < TJ ≤ 85°C During EEPROM Write Operations l 440 4100 ms Digital Inputs SCL, SDA, RUN, GPIO VIH Input High Threshold Voltage SCL, SDA, RUN, GPIO l 1.35 V VIL Input Low Threshold Voltage SCL, SDA, RUN, GPIO l 0.8 V VHYST Input Hysteresis SCL, SDA 0.08 V CPIN Input Capacitance 10 pF Digital Input WP IPUWP Input Pull-Up Current WP 10 µA Open-Drain Outputs SCL, SDA, GPIO, ALERT, RUN, SHARE_CLK, PGOOD VOL Output Low Voltage ISINK = 3mA l 0.4 V Digital Inputs SHARE_CLK, WP VIH Input High Threshold Voltage l 1.5 1.8 V VIL Input Low Threshold Voltage l 0.6 1.0 V Leakage Current SDA, SCL, ALERT, RUN IOL Input Leakage Current 0V ≤ VPIN ≤ 5.5V l ±5 µA Leakage Current GPIO, PGOOD IGL Input Leakage Current 0V ≤ VPIN ≤ 3.6V l ±2 µA Digital Filtering of GPIO IFLTG Input Digital Filtering GPIO 3 µs Digital Filtering of RUN IFLTG Input Digital Filtering RUN 10 µs PMBus Interface Timing Characteristics fSCL Serial Bus Operating Frequency l 10 400 kHz tBUF Bus Free Time Between Stop and Start l 1.3 µs tHD,STA Hold time After Repeated Start Condition. After this Period, the First Clock is Generated l 0.6 µs tSU,STA Repeated Start Condition Setup Time l 0.6 µs tSU,STO Stop Condition Setup Time l 0.6 µs tHD,DAT Data Hold Time Receiving Data Transmitting Data l l 0 0.3 0.9 µs µs |
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