LTM4677 datasheet(14/116 Pages) AD

14 / 116 page

LTC3883/LTC3883-1

Rev. F

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PIN FUNCTIONS

VIN_SNS (Pin 1): Input Current Sense Comparator Input.

The (–) input to the input current comparator is normally

connected to the supply side of the input current sense

resistor through a 100Ω resistor. If the input current

sense amplifier is not used, this pin must be shorted to

the IIN_SNS and VIN pins.

IIN_SNS (Pin 2): Input Current Sense Comparator Input.

The (+) input to the input current comparator is normally

connected to the power stage side of the input current

sense resistor through a 100Ω resistor. If the input current

sense amplifier is not used, this pin must be shorted to

the VIN_SNS and VIN pins.

ISENSE+ (Pin 3): Current Sense Comparator Input. The (+)

input to the current comparator is normally connected

to the DCR sensing network or current sensing resistor.

ISENSE– (Pin 4): Current Sense Comparator Input. The (–)

input is connected to the output.

SYNC (Pin 5): External Clock Synchronization Input and

Open-Drain Output Pin. If an external clock is present at

this pin, the switching frequency will be synchronized to

the external clock. If clock master mode is enabled, this

pin will pull low at the switching frequency with a 500ns

pulsewidthtoground.Aresistorpull-upto3.3Visrequired

in the application.

SCL (Pin 6): Serial Bus Clock Input. A pull-up resistor to

3.3V is required in the application.

SDA (Pin 7): Serial Bus Data Input and Output. A pull-up

resistor to 3.3V is required in the application.

ALERT (Pin 8): Open-Drain Digital Output. Connect the

SMBALERT signal to this pin.

GPIO (Pin 9): Digital Programmable General Purpose

Inputs and Outputs. Open-drain output.

PGOOD(Pin10):DigitalPowerGoodIndicator.Open-drain

output. The PGOOD pin is based on comparator outputs

and may be used for sequencing.

RUN (Pin 11): Enable Run Input. Logic high on this pin

enables the controller. This pin requires a resistor pull-

up to 3.3V in the application and should be driven by an

open-drain digital output.

DNC (Pins 12, 16): Do Not Connect to This Pin.

ASEL (Pin 13): Serial Bus Address Configuration Input.

Connect a ±1% resistor divider between the chip VDD25

ASELandGNDinordertoselectthe4LSBsoftheserialbus

interface address. A resistor divider on ASEL is required

if there are more than one LTC3883 on the same board

to assure the user can independently program each IC. If

the pin is left open, the IC will use the value programmed

in the NVM. Minimize capacitance when the pin is open

to assure accurate detection of the pin state.

FREQ_CFG (Pin 14): Frequency or Phase Set/Select Pin.

Connect a ±1% resistor divider between the chip VDD25

FREQ_CFGandGNDinordertoselectswitchingfrequency

or phase. If the pin is left open, the IC will use the value

programmed in the NVM. Minimize capacitance when the

pin is open to assure accurate detection of the pin state.

VOUT_CFG (Pin 15): Output Voltage Select Pin. Connect a

±1% resistor divider between the chip VDD25, VOUT_CFG

and SGND in order to select output voltage. This voltage

can be adjusted with the VTRIM_CFG pins. If the pin is left

open, the IC will use the value programmed in the NVM.

Minimize capacitance when the pin is open to assure ac-

curate detection of the pin state.

VTRIM_CFG (Pin 17): Voltage Trim Select Pin. Connect a

±1% resistor divider between the chip VDD25, VTRIM_CFG

and SGND in order to adjust the output voltage set point.

The VTRIM_CFG settings in conjunction with the VOUT_CFG

setting adjusts the voltage set point. If the pin is left open,

the IC will either not modify the VOUT_CFG setting or use

NVM. Minimize capacitance when the pin is open to assure

accurate detection of the pin state.

VDD25 (Pin 18): Internally Generated 2.5V Power Supply

Output. Bypass this pin to GND with a low ESR 1μF capaci-

tor. Do not load this pin with external current.

WP (Pin 19): Write Protect Pin Active High. An internal

10µA current source pulls the pin to VDD33. If WP is high,

the PMBus writes are restricted.

SHARE_CLK (Pin 20): Share Clock, Bidirectional Open-

Drain Clock Sharing Pin. Nominally 100kHz. Used to syn-

chronize the timing between multiple LTC3883s. Tie all the

SHARE_CLK pins together. All LTC3883s will synchronize

to the fastest clock. An equivalent pull-up resistance of

5.49k to VDD33 is required.

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