GC5316 datasheet(35/75 Pages) TI

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GC5316

SLWS154A − JANUARY 2004 − REVISED MARCH 2004

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Table 9. Programming

VARIABLE

DESCRIPTION

cic_interp_decim(4:0)

The CIC interpolation is Ncic = cic_interp_decim + 1. This ratio applies to both A and B

channels of the DUC block in CDMA mode. Legal values for cic_interp_decim are 3 to 31.

cic_scale_a(4:0)

The shift value for the A channel. A value of 0 is no shift, each increment in value increases

the amplitude of the shifter output by a factor of 2.

cic_scale_b(4:0)

The shift value for the B channel. A value of 0 is no shift, each increment in value increases

the amplitude of the shifter output by a factor of 2.

cic_m2_ena_a(5:0)

Sets the differential delay value M for each of the CIC subtractor stages for the A channel.

Cic_m2_en_a(0) controls m1, cic_m2_en_a(5) controls the m5. A set bit programs the

differential delay M to 2, if cleared M is programmed to 1.

cic_m2_ena_b(5:0)

Sets the differential delay value M for each of the CIC subtractor stages for the B channel.

ssel_cic(2:0)

Sync source

cic_auto_flush_dis(3:0)

When set disables the CIC auto−flush. Bits {0, 1, 2, 3} correspond to CICs for {CDMA−A I

data, CDMA−A Q data, CDMA−B I data, CDMA−B Q data} sections.

cic_auto_flush_test(3:0)

On rising forces a CIC overflow error. Program to 0 then to 1 for edge to occur. Bits {0, 1, 2,

3} correspond to CICs for {CDMA−A I data, CDMA−A Q data, CDMA−B I data, CDMA−B Q

data} sections.

cic_auto_flush_clear(3:0)

On rising clears a CIC overflow condition. Program to 0 then to 1 for edge to occur. Bits {0,

1, 2, 3} correspond to CICs for {CDMA−A I data, CDMA−A Q data, CDMA−B I data,

CDMA−B Q data} sections.

3.1.6 Transmit Adjustable Channel Delay

Figure 29. Transmit Delay Adjustment

The transmit channel delay adjust function permits the user to add a programmable time delay in each of the

upconverter paths. This is used to calibrate multiple transmit channels in the overall base transceiver system. The

adjustable delay compensates for analog elements external to the digital upconversion such as cables, splitters,

analog upconverters, filters, etc., and to compensate for differential delay between channels within the GC5316.

There is an additional delay of two output sample times for each pair of DUC blocks to allow for pipelining of the

sumchain (specifically, DUC0 and 1 have the same delay, DUCs 2 and 3 are the same but are two output sample

times larger than DUC0 and 1, etc.).

There are two elements that need to be considered with respect to programming the delay: the decimation and delay

memory blocks.

The decimation function reduces the sample rate from txclk to the desired output rate. The decimation amount is set

by parameter (tadj_interp_decim+1). Phasing of the decimation operation permits finer delay resolution. The 3-bit delay

offset parameter permits finer delay resolution in steps of the reciprocal of the GC5316’s tx clock rate. At 122.88 MHz,

this would equate to a time delay resolution of 8.1 ns (1/32 chip for UMTS, 1/100 of a chip for CDMA). The offset

may be set from 0 to tadj_interp_decim.

The coarse delay adjustment is done using a delay memory of 64 memory locations by 36 bits (18 for I and 18 for

Q). Read and write pointers in the memory are separated by tadj_offset_coarse. Data written into a location is read

out tadj_offset_coarse output sample times later. 24 locations are needed to equalize the time delay within the

GC5316 for various channels. The remaining 40 locations provide a total delay of up to about 1.3

µs when the DUC

output data rate is 30.72 MSPS.

A sync signal permits the decimation operation to be synchronized over multiple channels.

GC5316 Datasheet(PDF) 35 Page - Texas Instruments

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