GC5316 datasheet(19/75 Pages) TI

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GC5316

SLWS154A − JANUARY 2004 − REVISED MARCH 2004

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For CDMA mode, the integration time is slightly longer. The power read in CDMA mode with a dc input is:

A power: [ I2(X x 4 + 1) + Q2(X x 4 + 0) ]2−23 Note that one Q sample is missing from the integration.

B power: [ I2(X x 4 + 1) + Q2(X x 4 + 1) ]2−23

Where X is the integration count.

Table 17. Programming

FIELD

DESCRIPTION

pmeter_result_a_lsb(15:0)

Lower 16 bits of the A DDC channel power measurement result.

pmeter_result_a_msb (31:16)

Upper 16 bits of the A DDC channel power measurement result.

pmeter_result_b_lsb (15:0)

Lower 16 bits of the B DDC channel power measurement result. Only available for CDMA.

pmeter_result_b_msb (31:16)

Upper 16 bits of the B DDC channel power measurement result. Only available for CDMA.

pmeter_integration_ddc(15:0)

Integration time = 4(1+pmeter_count_ddc).

pmeter_sync_delay_ddc(7:0)

Start delay from sync = 3 + pmeter_sync_delay_ddc.

pmeter_interval_ddc(7:0)

Interval time = 1024(pmeter_interval_ddc+1). Interval time must be greater than (not equal) integration time.

ssel_pmeter(2:0)

Sync source options

pmeter_sync_disable

Turns off the sync to the channel power meter. This can be used to individually turn off syncs to a channels

power meter, while still having syncs to other power meters on the chip.

2.5

Receive Gain and AGC

The receive AGC can be used as a simple gain or as a flexible AGC.

2.5.1 Receive Simple Gain

The receive AGC can be used as simple gain by freezing the AGC accumulator at its current level, then clearing the

current value. This is done by setting the agc_clear and agc_freeze bits. The output can be rounded from 3 to 18 bits

using agc_rnd or the full 25 bits can be output by setting agc_rnd_disable.

2.5.2 Receive AGC

Shift Select

Delay

Freeze

Valid

Under Limit

Over Limit

Accumulate

Limit

Under/Over

Detect

Magnitude

Compare

Valid

Clear

Shift

Threshold

Ucnt

Ocnt

Dblw

Dabv

Dzro

Dsat

Ucnt

Ocnt

7 integer & 12 F ractional

7integer &

12 F ractional

Valid

Gain

7integer &

12 Fractional

18 data +

7overflow

Round

A(t) = gain adjust

Zero Mask

Input

Output

S= +−1, D= 4bit shift

(up to 25bitsin AGC bypass mode)

Figure 16. AGC Block Diagram

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