GC5316 datasheet(12/75 Pages) TI

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GC5316

SLWS154A − JANUARY 2004 − REVISED MARCH 2004

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Each of the 24 CDMA DDC blocks can be loaded with unique phase offset words.

Various synchronization signals are available which are used to synchronize the NCOs of all channels with respect

to each other. Frequency sync (ssel_freq) and phase offset sync (ssel_phase) determine when frequency and phase

offset changes occur. For example, generating a frequency sync after programming the two frequency words causes

the NCO (or multiple NCOs) to change frequency at that time, rather than after each of the two frequency words are

programmed over the control bus. Note that the frequency and phase words are not loaded into the working register

until their respective sync’s are received. The zero phase sync signal (ssel_nco) is used to force the sine and cosine

oscillators to their zero phase state. Note that this is an instantaneous phase jump, so the ssel_nco should only be

issued when resetting a channel. Dither sync (ssel_dither) can be used to synchronize the dither generators of

multiple NCOs. This is normally only required for applications that are performing bit match testing. The NCOs used

in the transmit section are identical to what is described for the receive section. Note that there is one set of sync’s

provided for each DDC. When one DDC is used to process two CDMA signal the sync’s are shared between them.

Table 11. Programming

VARIABLE

DESCRIPTION

ssel_nco(2:0)

Sync source for NCO accumulator reset

ssel_dither(2:0)

Sync source for NCO dither reset

ssel_freq(2:0)

Sync source for NCO frequency register loading

ssel_phase(2:0)

Sync source for NCO phase register loading

2.3.3 Receive Filtering and Decimation

The purpose of the receive filter chain is to isolate the signal of interest (and reject all other others) that has been

previously translated to baseband via the mixer and NCO. The overall decimation through the chain also needs to

be considered. The goal, generally, is to output the isolated signal at a rate that is twice (2X) the signal’s chip rate.

For UMTS, this would be 7.68 MSPS. For CDMA the output rate should be 2.4576 MSPS.

Receive filtering and decimation is performed in several stages:

D Zero padding to interpolate the input sample rate if needed up to the rxclk rate

D High rate decimation (4 to 32) using a six stage cascade-integrate comb filter (CIC)

D Decimate by two compensation filtering using the programmable compensating FIR filter (CFIR)

D Decimate by one pulse-shape filtering via the programmable FIR filter (PFIR)

CF IR F ilter

D ecby2

De la y

Adjust

PFI R Filter

Decby1

Six Stage

CIC Filter

Dec 4 −32

Zero Pad

From

Mixer

Figure 11. DDC Filter Chain

The following table contains some examples listing the decimation and sample rates at the output of each block for

UMTS and CDMA standards at input sample rates of 61.44 MSPS and 15.36 MSPS, assuming the GC5316 is

clocked at 122.88 MHz.

Table 12. Example UMTS and CDMA2000 DDC Receive Modes

INPUT

SAMPLE

RATE

(MSPS)

ZEROS

ADDED

ZERO PAD

OUTPUT

RATE

(MSPS)

CIC

DECIMATION

CIC

OUTPUT

RATE

(MSPS)

CFIR

DECIMATION

CFIR

OUTPUT

RATE

(MSPS)

PFIR

DECIMATION

PFIR

OUTPUT

RATE

(MSPS)

UMTS

61.44

122.88

15.36

7.68

UMTS

15.36

122.88

15.36

7.68

CDMA

61.44

122.88

4.9152

2.4576

CDMA

15.36

122.88

4.9152

2.4576

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