GC5316 datasheet(28/75 Pages) TI

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GC5316

SLWS154A − JANUARY 2004 − REVISED MARCH 2004

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When the block is configured for a single UMTS channel, the txin_a is for I data, and txin_b carries the Q data. The

most significant bit is sent first.

The four pin mode is a less common mode. It employs another two pins from the adjacent (2k+1) DUC, sacrificing

the use of that DUC in order to allow reduced datarate on the serial pins. The I data (Imsb, Imsb−1) are carried on

txin _(2k) _a and txin _(2k)_b, while the Q data (Qmsb Qmsb−1) is carried on txin _(2k+1) _a and txin _(2k+1) _b.

Each pair of DUC blocks 2k and 2k+1 share the clock division, frame delay, sync generation, and a frame strobe

output pin.

A programmable clock divider circuit can be used to specify the serial bit rate with respect to txclk. The divider is

programmed as txclk / (1+serp_trans_clkdiv). The clock divider circuit is synchronized using a general sync block

discussed in another section of this document.

The frame sync interval can be programmed from 1 to 127 bits (which are divided clocks).

The number of bits in a word is set as (serp_tran_bits+1).

The frame strobe is an output from the gc5316 that indicates when the msb is expected. The frame strobe can be

programmed to arrive from 0 to 3-bit clocks ahead of when the msb is expected via the serp_tran_fsdel parameter.

The source must transmit all of its data before the next frame strobe is generated. Use of the frame strobe is optional

in that when the msb is expected is determined by the sync (ssel_serial).

The parameter chosen must satisfy the following constraints:

D serp_tran_fsinv x (serp_tran_clkdiv+1) = 4 x (cic_interp_decim+1)

D serp_tran_fsinv >= (serp_tran_bits+1)2 for CDMA mode

D serp_tran_fsinv >= (serp_tran_bits+1) for UMTS mode

D serp_tran_fsinv >= (serp_tran_bits+1)0.5 for four−pin mode

NOTE:For half-rate data (when serp_tran_clkdiv= 1), the MSB of the input data stream is captured on the 4th rising edge

of txclk, after txsync occurs. For full-rate data (when serp_tran_clkdiv= 0), the MSB of the input data stream is captured

on the 3rd rising edge of txclk, after txsync occurs.

Figure 23 shows the transmit serial input timing.

txclk

txsync

2txclk

tx_sync_out

MSB

MSB−1

2txclk

(programmable)

(serp_tran_fsdel= 0

serp_tran_clkdiv= 1)

txin

(serial input data)

tsu

tpd

Figure 23. Transmit Serial Input Timing

GC5316 Datasheet(PDF) 28 Page - Texas Instruments

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