TPS62933O datasheet(3/47 Pages) TI

3 / 47 page

5 Device Comparison Table

PART NUMBER

OUTPUT CURRENT

PFM OR FCCM OR OOA SS OR PG PIN

STATUS

TPS62933

3 A

PFM

Released

TPS62932

2 A

PFM

To be released

TPS62933F

3 A

FCCM

To be released

TPS62933O

3 A

OOA

To be released

TPS62933P

3 A

PFM

To be released

6 Pin Configuration and Functions

VIN

GND

BST

Figure 6-1. 8-Pin SOT583 DRL Package (Top View)

Table 6-1. Pin Functions

TYPE(1)

DESCRIPTION

NAME

NO.

Frequency programming input. Float for 500 kHz, tie to GND for 1.2 MHz, or connect to an

RT timing resistor. See Section 8.3.5 for details.

Enable input to converter. Driving EN high or leaving this pin floating enables the converter.

An external resistor divider can be used to implement an adjustable VIN UVLO function.

VIN

Supply input terminal to internal LDO and high-side FET. Input bypass capacitors must be

directly connected to this pin and GND.

GND

Ground terminal. Connected to the source of the low-side FET as well as the ground

terminal for the controller circuit. Connect to system ground and the ground side of CIN

and COUT. The path to CIN must be as short as possible.

Switching output of the convertor. Internally connected to the source of the high-side FET

and drain of the low-side FET. Connect to power inductor.

BST

Bootstrap capacitor connection for high-side FET driver. Connect a high-quality, 100-nF

ceramic capacitor from this pin to the SW pin.

Soft-start and tracking input. An external capacitor connected to this pin sets the internal

voltage reference rising time. See Section 8.3.7 for details. A minimum 6.8-nF ceramic

capacitor must be connected at this pin, which sets the minimum soft-start time to

approximately 1 ms. Do not float.

Output feedback input. Connect FB to the tap of an external resistor divider from the output

to GND to set output voltage.

(1)

A = Analog, P = Power, G = Ground

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TPS62933

SLUSEA4A – JUNE 2021 – REVISED DECEMBER 2021

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