TPS62933O datasheet(36/47 Pages) TI

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11 Layout

11.1 Layout Guidelines

The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout

can disrupt the operation of a good schematic design. Even if the converter regulates correctly, bad PCB layout

can mean the difference between a robust design and one that cannot be mass produced. Furthermore, the

EMI performance of the converter is dependent on the PCB layout to a great extent. In a buck converter, the

most critical PCB feature is the loop formed by the input capacitors and power ground, as shown in Figure 11-1.

This loop carries large transient currents that can cause large transient voltages when reacting with the trace

inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because of this,

the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic

inductance.

TI recommends a 2-layer board with 2-oz copper thickness of top and bottom layer, and proper layout provides

low current conduction impedance, proper shielding, and lower thermal resistance. Figure 11-2 and Figure 11-3

show the recommended layouts for the critical components of the TPS62933.

• Inductor, input/output capacitors, and the IC should be placed on the same layer.

• The input/output capacitors should be placed as close as possible to the IC. The VIN and GND traces should

be as wide as possible and provide sufficient vias on them to minimize trace impedance. The wide areas are

also of advantage from the view point of heat dissipation.

• A 0.1-µF ceramic decoupling capacitor or several should be placed as close as possible to VIN and GND pins

which is key to EMI reduction.

• Keep the SW trace as physically short and wide as practical to minimize radiated emissions.

• BST capacitor and resistor should be placed close to BST pin and SW node, > 10-mil width trace is

recommended to reduce the parasitic inductance.

• The feedback divider should be placed as close as possible to the FB pin, > 10-mil width trace is

recommended for heat dissipation. A separate VOUT trace should be connected to the upper feedback

resistor, the voltage feedback loop should be placed away from the high-voltage switching trace, and

preferably has ground shield.

• SS capacitor and RT resistor should be placed close to the IC and routed with minimal lengths of trace, >

10-mil width trace is recommended for heat dissipation.

VIN

GND

KEEP

CURRENT

LOOP

SMALL

Figure 11-1. Current Loop With Fast Edges

TPS62933

SLUSEA4A – JUNE 2021 – REVISED DECEMBER 2021

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TPS62933O Datasheet(PDF) 36 Page - Texas Instruments