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DP8500 Datasheet(PDF) 18 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP8500
Description  DP8520A/DP8521A/DP8522A microCMOS Programmable 256k/1M/4M Video RAM Controller/Drivers
PDF  70 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP8500 Datasheet(HTML) 18 Page - National Semiconductor (TI)

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40 Refresh Options (Continued)
43 EXTENDING REFRESH
The programmed number of periods of CLK that refresh
RASs are asserted can be extended by one or multiple peri-
ods of CLK Only the all RAS (with or without error scrub-
bing) type of refresh can be extended To extend a refresh
cycle the input extend refresh EXTNDRF must be assert-
ed before the positive edge of CLK that would have negated
all the RAS outputs during the refresh cycle and after the
positive edge of CLK which starts all RAS outputs during the
refresh as shown in
Figure 13 This will extend the refresh to
the next positive edge of CLK and EXTNDRF will be sam-
pled again The refresh cycle will continue until EXTNDRF is
sampled low on a positive edge of CLK
44 CLEARING THE REFRESH ADDRESS COUNTER
The refresh address counter can be cleared by asserting
RFSH while DISRFSH is negated as shown in
Figure 14a
This can be used prior to a burst refresh of the entire memo-
ry array By asserting RFSH one period of CLK before
DISRFSH is asserted and then keeping both inputs assert-
ed the DP8520A21A22A will clear the refresh address
counter and then perform refresh cycles separated by the
programmed value of precharge as shown in
Figure 14b An
end-of-count signal can be generated from the Q VRAM
address outputs of the DP8520A21A22A and used to ne-
gate RFSH
45 CLEARING THE REFRESH REQUEST CLOCK
The refresh request clock can be cleared by negating
DISRFSH and asserting RFSH for 500 ns one period of the
internal 2 MHz clock as shown in
Figure 15 By clearing the
refresh request clock the user is guaranteed that an inter-
nal refresh request will not be generated for approximately
15 ms one refresh clock period from the time RFSH is neg-
ated This action will also clear the refresh address counter
TLF9338 – 19
FIGURE 13 Extending Refresh with the Extend Refresh (EXTNDRF) Input
TLF9338 – 20
FIGURE 14a Clearing the Refresh Address Counter
TLF9338 – 21
FIGURE 14b Clearing the Refresh Counter during Burst
TLF9338 – 22
FIGURE 15 Clearing the Refresh Request Clock Counter
18



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