DP8500 datasheet(19/70 Pages) NSC

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50 Port A Wait State Support

Wait states allow a CPU’s access cycle to be increased by

one or multiple CPU clock periods The wait or ready input is

named differently by CPU manufacturers However any

CPU’s wait or ready input is compatible with either the WAIT

or DTACK output of the DP8520A21A22A The user de-

termines whether to program WAIT or DTACK (R7) and

which value to select for WAIT or DTACK (R2 R3) depend-

ing upon the CPU used and where the CPU samples its wait

input during an access cycle

The decision to terminate the CPU access cycle is directly

affected by the speed of the VRAMs used The system de-

signer must ensure that the data from the VRAMs will be

present for the CPU to sample or that the data has been

written to the VRAM before allowing the CPU access cycle

to terminate

The insertion of wait states also allows a CPU’s access cy-

cle to be extended until the VRAM access has taken place

The DP8520A21A22A insert wait states into CPU access

cycles due to guaranteeing precharge time refresh current-

ly in progress user programmed wait states the WAITIN

signal being asserted and GRANTB not being valid

(DP8522A only) If one of these events is taking place and

the CPU starts an access the DP8520A21A22A will insert

wait states into the access cycle thereby increasing the

length of the CPU’s access Once the event has been com-

pleted the DP8520A21A22A will allow the access to take

place and stop inserting wait states

There are six programming bits R2 – R7 an input WAITIN

and an output that functions as WAIT or DTACK

51 WAIT TYPE OUTPUT

With the R7 address bit negated during programming the

user selects the WAIT output As long as WAIT is sampled

asserted by the CPU wait states (extra clock periods) are

inserted into the current access cycle as shown in

Figure

16 Once WAIT is sampled negated the access cycle is

completed by the CPU WAIT is asserted at the beginning of

a chip selected access and is programmed to negate a

number of positive edges andor negative levels of CLK

from the event that starts the access WAIT can also be

programmed to function in pageburst mode applications

Once WAIT is negated during an access and the ECAS

inputs are negated with AREQ asserted WAIT can be pro-

grammed to toggle following the ECAS inputs Once AREQ

is negated ending the access WAIT will stay negated until

the next chip selected access For more details about WAIT

Type Output see Application Note AN-773

52 DTACK TYPE OUTPUT

With the R7 address bit asserted during programming the

user selects the DTACK type output As long as DTACK is

sampled negated by the CPU wait states are inserted into

the current access cycle as shown in

Figure 17 Once

DTACK is sampled asserted the access cycle is completed

by the CPU DTACK which is normally negated is pro-

grammed to assert a number of positive edges andor neg-

ative levels from the event that starts RAS for the access

DTACK can also be programmed to function during page

burst mode accesses Once DTACK is asserted and the

ECAS inputs are negated with AREQ asserted DTACK can

be programmed to negate and assert from the ECAS inputs

toggling to perform a pageburst mode operation Once

AREQ is negated ending the access DTACK will be negat-

ed and stays negated until the next chip selected access

For more details about DTACK Type Output see Applica-

tion Note AN-773

TLF9338 – 23

FIGURE 16 WAIT Type Output

TLF9338 – 44

FIGURE 17 DTACK Type Output

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