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DP8500 Datasheet(PDF) 39 Page - National Semiconductor (TI) |
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DP8500 Datasheet(HTML) 39 Page - National Semiconductor (TI) |
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39 / 70 page  90 Programming and Resetting (Continued) 93 EXTERNAL RESET At power up if the internal power up reset worked all inter- nal latches and flip-flops are cleared The power up state is entered by asserting ML and DISRFSH for 16 positive edg- es of CLK After 16 clocks if the user negates DISRFSH before negating ML as shown in Figure 51 ML negated will program the chip If ML is negated before or at the same time as DISRFSH as shown in Figure 52 the chip will not be programmed After the chip is programmed the 60 ms ini- tialization period will be entered into if this is the first pro- gramming after power up or reset The user must perform an external reset before programming the DP8520A21A 22A TLF9338 – A2 FIGURE 51 Chip Reset and Programmed TLF9338 – A3 FIGURE 52 Chip Reset but Not Programmed 39 |
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