DP8500 datasheet(36/70 Pages) NSC

36 / 70 page

80 RAS and CAS Configuration Modes (Continued)

85 PAGEBURST MODE

In a static column page or burst mode system the least

significant bits must be tied to the column address in order

to ensure that the pageburst accesses are to sequential

memory addresses as shown in

Figure 44 In a nibble mode

system the two least significant address bits (A2 A3) must

be tied to the highest row and column address inputs (de-

pends on VRAM size) to ensure that the toggling bits of

nibble mode VRAMs are to sequential memory addresses

The ECAS inputs may then be toggled with the DP8520A

21A22A’s address latches in fall-through mode

while

AREQ is asserted The ECAS inputs can also be used to

select individual bytes When using nibble mode VRAMS

the third and fourth address bits can be tied to the bank

select inputs to perform memory interleaving In page or

static column modes the two address bits after the page

size can be tied to the bank select inputs to select a new

bank if the page size is exceeded

TLF9338 – 95

See table below for row column

bank address bit map A0A1 are used for byte addressing in this example

Addresses

Nibble Mode

Page ModeStatic Column Mode Page Size

256 BitsPage

512 BitsPage

1024 BitsPage

2048 BitsPage

Column

R9 C9 e A2 A3

C0 – 7 e A2–9

C0–8 e A2–10

C0–9 e A2–11

C0–10 e A2–12

Address

C0 – 8 e X

C8–10 e X

C910 e X

C10 e X

Row

Address

A10

A11

A12

A13

A11

A12

A13

A14

Assuming 1 M-bit Vrams are being used

Assume that the least significant address bits are used for byte addressing Given a 32-bit system A0A1 would be

used for byte addressing

X e DON’T CARE the user can do as he pleases

FIGURE 44 Page Static Column Nibble Mode System

DP8500 Datasheet(PDF) 36 Page - National Semiconductor (TI)

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