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DP8500 Datasheet(PDF) 20 Page - National Semiconductor (TI) |
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DP8500 Datasheet(HTML) 20 Page - National Semiconductor (TI) |
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20 / 70 page  50 Port A Wait State Support (Continued) 53 WAIT STATE SUPPORT FOR VIDEO RAM SHIFT REGISTER LOAD OPERATIONS FOR PORT A If using the DP8520A21A22A in a system using video VRAMs the CPU that controls loading the Video RAM shift register must be connected to Port A The input AVSRLRQ asserts signaling an advanced request for a Video RAM shift register load operation Sometime later the input VSRL asserts signifying that the transfer cycle has started and this action causes the DT OE output to transfer low VSRL asserting also asserts WAIT (keeps DTACK negated) and will then insert wait states into the transfer cycle The trans- fer cycle is completed from either VSRL negating or four clocks from VSRL asserting The first event of these two to take place causes WAIT to negate (DTACK to assert) imme- diately or one half system clock period later depending on how the user had programmed WAIT to end (DTACK to start) during a non-burst type of access The wait logic is intimately connected to the DP8520A21A22A graphics functions and the WAIT output functions the same as the DT OE output (see Figure 18 ) TLF9338 – 74 FIGURE 18 Wait State Timing during a VRAM Transfer Cycle (WAIT Programmed as OT WAIT Sampled at the ‘‘T3’’ Rising Clock Edge) 20 |
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