DP8500 datasheet(28/70 Pages) NSC

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70 Additional Access Support Features

To support the different modes of accessing the DP8520A

21A22A have multiple access features These features al-

low the user to take advantage of CPU or VRAM functions

These additional features include address latches and col-

umn increment for pageburst mode support address pipe-

lining to allow a new access to start to a different bank of

VRAM after CAS has been asserted and the column ad-

dress hold time has been met and delay CAS to allow the

user with a multiplexed bus to ensure valid data is present

before CAS is asserted

71 ADDRESS LATCHES AND COLUMN INCREMENT

The address latches can be programmed through program-

ming bit B0 to either latch the address or remain perma-

nently in fall-through mode If the address latches are used

to latch the address the rising edge of ALE in Mode 0

places the latches in fall-through Once ALE is negated the

address present on the row column and bank inputs is

latched In Mode 1 the address latches are in fall-through

mode until ADS is asserted ADS asserted latches the ad-

dress

Once the address is latched the column address can be

incremented with the input COLINC With COLINC asserted

the column address is incremented If COLINC is asserted

with all of the bits of the column address asserted the col-

umn address will return to zero COLINC can be used for

sequential accesses of static column VRAMs COLINC can

also be used with the ECAS inputs to support sequential

accesses to page mode VRAMs as shown in

Figure 29

COLINC should only be asserted when a refresh is not in

progress as indicated by RFIP if programmed being ne-

gated during an access since this input functions as an ex-

tend refresh when a refresh is in progress

The address latches function differently with the DP8522A

The DP8522A will latch the address of the currently granted

port If Port A is currently granted the address will be

latched as described in Section 71 If Port A is not granted

and requests an access the address will be latched on the

first or second positive edge of CLK after GRANTB has

been negated depending on the programming bits R0 R1

For Port B if GRANTB is asserted the address will be

latched with AREQB asserted If GRANTB is negated the

address will latch on the first or second positive edge of

CLK after GRANTB is asserted depending on the program-

ming bits R0 R1

72 ADDRESS PIPELINING

Address pipelining is the overlapping of accesses to differ-

ent banks of VRAM If the majority of successive accesses

are to a different bank the accesses can be overlapped

Because of this overlapping the cycle time of the VRAM

accesses are greatly reduced The DP8520A21A22A can

be programmed to allow a new row address to be placed on

the VRAM address bus after the column address hold time

has been met At this time a new access can be initiated

with ADS or ALE depending on the access mode while

AREQ is used to sustain the current access The DP8522A

supports address pipelining for Port A only This mode can

not be used with page static column or nibble modes of

operations because the VRAM column address is switched

back to the row address after CAS is asserted This mode is

programmed through address bit R8 (see

Figures 30 and

31 )

During address pipelining in Mode 0 shown in

Figure 32

ALE cannot be pulsed high to start another access until

AREQ has been asserted for the previous access for at

least one period of CLK DTACK if programmed will be

negated once AREQ is negated WAIT if programmed to

insert wait states will be asserted once ALE and CS are

asserted

In Mode 1 shown in

Figure 33 ADS can be negated once

AREQ is asserted After meeting the minimum negated

pulse width for ADS ADS can again be asserted to start a

new access DTACK if programmed will be negated once

AREQ is negated WAIT if programmed will be asserted

once ADS is asserted

In either mode with either type of wait programmed the

DP8520A21A22A will still delay the access for precharge

if sequential accesses are to the same bank or if a refresh

takes place

DP8500 Datasheet(PDF) 28 Page - National Semiconductor (TI)

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