DP8500 datasheet(10/70 Pages) NSC

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30 Port A Access Modes

The DP8520A21A22A have two general purpose access

modes With one of these modes any microprocessor can

be interfaced to VRAM A Port A access to VRAM is initiated

by two input signals ADS (ALE) and CS The access is al-

ways terminated by one signal AREQ These input signals

should be synchronous to the input clock CLK One of

these access modes is selected at programming through

the B1 input signal In both modes once an access has

been requested by CS and ADS (ALE) the DP8522A will

guarantee the following

The DP8520A21A22A will have the row address valid to

the VRAMs’ address bus Q0 – 8 9 10 given that the row

address setup time to the DP8520A21A22A was met

The DP8520A21A22A will bring the appropriate RAS or

RASs low

The DP8520A21A22A will guarantee the minimum row

address hold time before switching the internal multiplexor

to place the column address on the VRAM address bus

Q0 – 8 9 10

The DP8520A21A22A will guarantee the minimum col-

umn address setup time before asserting the appropriate

CAS or CASs

The DP8520A21A22A will hold the column address valid

the minimum specified column address hold time in address

pipelining mode and will hold the column address valid the

remainder of the access in non-pipelining mode

The chip includes a WIN pin to signify a write operation to

the DP8520A21A22A When asserted WIN will cause

CAS to delay to the next positive clock edge if address bit

C9 is asserted during programming When negated WIN will

cause the DT OE output to follow the CAS outputs for a

read access if ECAS0 is negated during programming WE

write enable must be externally gated from the processor to

the VRAM as there is no output pin from the WIN input pin

available on chip

31 ACCESS MODE 0

Access Mode 0 shown in

Figure 5a is selected by negating

the input B1 during programming This access mode allows

accesses to VRAM to always be initiated from the positive

edge of the system input clock CLK To initiate a Mode 0

access ALE is pulsed high and CS is asserted Pulsing ALE

high and asserting CS sets an internal latch which requests

an access If the precharge time from the last access or

VRAM refresh had been met and a refresh of VRAM a Port

B access or a VRAM transfer cycle was not in progress the

RAS or group of RASs would be initiated from the first posi-

tive edge of CLK If a VRAM refresh is in progress or pre-

charge time is required the controller will wait until these

events have taken place and assert RAS on the next posi-

tive edge of CLK

Sometime after the first positive edge of CLK after ALE and

CS have been asserted the input AREQ must be asserted

In single port applications once AREQ has been asserted

CS can be negated Once AREQ is negated RAS and

DTACK if programmed will be negated If ECAS0 is assert-

ed during programming CAS will be negated with AREQ If

ECAS0 was negated during programming a single CAS or

group of CASs will continue to be asserted after RAS has

been negated given that the appropriate ECASs inputs were

asserted as shown in

Figure 5b This allows the VRAM to

have data present on the data out bus while gaining RAS

precharge time ALE can stay asserted several periods of

CLK However ALE must be negated before or during the

period of CLK in which AREQ is negated

When performing address pipelining the ALE input cannot

be asserted to start another access until AREQ has been

asserted for at least one clock period of CLK for the present

access

32 ACCESS MODE 1

Access Mode 1 shown in

Figure 6a is selected by asserting

the input B1 during programming This mode allows access-

es which are not delayed by precharge Port B access

VRAM transfer cycle or refresh to start immediately from

the access request input ADS To initiate a Mode 1 access

CS is asserted followed by ADS asserted If the pro-

grammed precharge time from the last access or VRAM

refresh had been met and a refresh of the VRAM a Port B

access to the VRAM or a VRAM transfer cycle was not in

progress the RAS or group of RASs selected by program-

ming and the bank select inputs would be asserted from

ADS being asserted If a VRAM refresh a Port B access or

a VRAM transfer cycle is in progress or precharge time is

required the controller will wait until these events have tak-

en place and assert RAS or the group of RASs from the

next positive edge of CLK

When ADS is asserted or sometime after AREQ must be

asserted At this time ADS can be negated and AREQ will

continue the access Once AREQ is negated RAS and

DTACK if programmed will be negated If ECAS0 was as-

serted during programming

CAS will be negated with

AREQ If ECAS0 was negated during programming a single

CAS or group of CASs will continue to be asserted after

RAS has been negated given that the appropriate ECAS

inputs were asserted as shown in

Figure 6b This allows a

VRAM to have data present on the data out bus while gain-

ing RAS precharge time ADS can continue to be asserted

after AREQ has been asserted and negated however a new

access would not be started until ADS is negated and as-

serted again ADS and AREQ can be tied together in appli-

cations not using address pipelining

If address pipelining is programmed it is possible for ADS to

be negated after AREQ is asserted Once AREQ is assert-

ed ADS can be asserted again to initiate a new access

DP8500 Datasheet(PDF) 10 Page - National Semiconductor (TI)

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