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DP8500 Datasheet(PDF) 50 Page - National Semiconductor (TI) |
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DP8500 Datasheet(HTML) 50 Page - National Semiconductor (TI) |
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50 / 70 page  150 AC Timing Parameters DP8520ADP8521ADP8522A (Continued) Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 VRAMs per bank including trace capacitance (see Note 2) Two different loads are specified CL e 50 pF loads on all outputs except CL e 150 pF loads on Q0–8 9 and 10 or CH e 50 pF loads on all outputs except CH e 125 pF loads on RAS0–3 and CAS0–3 and CH e 380 pF loads on Q0–8 9 and 10 Common Parameter 8520A21A22A-25 Number Symbol Description CL CH Min Max Min Max 21 tPEDL ECAS Asserted to DTACK Asserted during a Burst Access 38 38 (Programmed as DTACK0) 22 tPEDH ECAS Negated to DTACK 38 38 Negated during a Burst Access 23 tSWCK WAITIN Asserted Setup to CLK 5 5 26 tPAQ Row Column Address Valid to 26 35 Q0 – 8 9 10 Valid 27 tPCINCQ COLINC Asserted to Q0 – 8 9 10 30 39 Incremented 28 tSCINEN COLINC Asserted Setup to ECAS 17 19 Asserted to Ensure tASC e 0ns 29a tSARQCK1 AREQ Negated Setup to CLK 37 37 High with 1 Period of Precharge 29b tSARQCK2 AREQ Negated Setup to CLK High with 15 15 l 1 Period of Precharge Programmed 30 tPAREQDH AREQ Negated to DTACK Negated 27 27 31 tPCKCAS CLK High to CAS Asserted 25 32 when Delayed by WIN 32 tSCADEN Column Address Setup to ECAS 14 16 Asserted to Guarantee tASC e 0 33 tWCINC COLINC Pulse Width 20 20 34a tPCKCL0 CLK High to CAS Asserted following 72 79 Precharge (tRAH e 15 ns tASC e 0 ns) 34b tPCKCL1 CLK High to CAS Asserted following 82 89 Precharge (tRAH e 25 ns tASC e 0 ns) 34c tPCKCL2 CLK High to CAS Asserted following 82 89 Precharge (tRAH e 25 ns tASC e 0 ns) 34d tPCKCL3 CLK High to CAS Asserted following 92 99 Precharge (tRAH e 25 ns tASC e 10 ns) 35 tCAH Column Address Hold Time 32 32 (Interleave Mode Only) 36 tPCQR CAS Asserted to Row Address 90 90 Valid (Interleave Mode Only) 37 tPCASDTH CAS Asserted to DT OE 14 24 Asserted for a VRAM Read Access 38 tPCASDTL CAS Negated to DT OE 14 24 Negated for a VRAM Read Access 50 |
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