DP8500 datasheet(37/70 Pages) NSC

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90 Programming and Resetting

The DP8520A21A22A must be programmed by one of

two possible programming sequences before it can be used

After power up the DP8520A21A22A must be externally

reset (see External Reset) before programming After pro-

gramming the DP8520A21A22A enters a 60 ms initializa-

tion period During this initialization period the DP8520A

21A22A performs refreshes about every 15 ms this makes

further VRAM warmup cycles unnecessary The chip can be

programmed as many times as the user wishes After the

first programming the 60 ms initialization period will not be

entered into unless the chip is reset Refreshes occur during

the 60 ms initialization period If ECAS0 was asserted during

programming the RFIP (RFRQ) pin will act as RFIP and will

be asserted throughout the initialization period otherwise

the pin will act like RFRQ and toggle every 13 ms–15 msin

conjunction with internal refresh requests If the user at-

tempts an access during the initialization period wait states

will be inserted into the access cycle until the initialization

period is complete and RAS precharge time has been met

The actual initialization time period is given by the following

formula

T e 4096 (Clock Divisor Select)

(Refresh Clock Fine Tune)

(DELCK Frequency)

91 MODE LOAD ONLY PROGRAMMING

MODE LOAD ML asserted enables an internal 23-bit pro-

grammable register To use this method the user asserts

ML enabling the internal programming register After ML is

asserted a valid programming selection is placed on the

address bus (and ECAS0) then ML is negated When ML is

negated the value on the address bus (and ECAS0) is

latched into the internal programming register and the

DP8520A21A22A is programmed as shown in

Figure 45

After ML is negated the DP8520A21A22A will enter the

60 ms initialization period only if this is the first programming

after power up or reset

Using this method a set of transceivers on the address bus

can be put at TRI-STATE

by the system reset signal A

combination of pull-up and pull-down resistors can be used

on the address inputs of the DP8520A21A22A to select

the programming values as shown in

FIgure 46

92 CHIP SELECTED ACCESS PROGRAMMING

The chip can also be programmed by asserting ML and per-

forming a chip selected access ADS (or ALE) is disabled

internally until after programming To program the chip using

this method ML is asserted After ML is asserted CS is

asserted and a valid programming selection is placed on the

address bus When AREQ is asserted the chip is pro-

grammed with the programming selection on the address

bus After AREQ is negated ML can be negated as shown

Figure 47

TLF9338 – 96

FIGURE 45 Mode Load Only Programming

TLF9338 – 97

Pull-Up or Pull-Down Resistors on Each Address Input

FIGURE 46 Programming during System Reset

DP8500 Datasheet(PDF) 37 Page - National Semiconductor (TI)

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