DP8500 datasheet(38/70 Pages) NSC

38 / 70 page

90 Programming and Resetting (Continued)

TLF9338 – 98

FIGURE 47 CS Access Programming

Using this method various programming schemes can be

used For example if extra upper address bits are available

an unused high order address bit can be tied to the signal

ML Using this method one need only write to a page of

memory thus asserting the high order bit and in turn pro-

gramming the chip as shown in

Figure 48

TLF9338 – 99

FIGURE 48 Programming the DP8520A21A22A

through the Address Bus Only

An IO port can also be used to assert ML After ML is

asserted a chip selected access can be performed to pro-

gram the chip After the chip selected access ML can be

negated through the IO port as shown in

Figure 49

TLF9338 – A0

FIGURE 49 Programming the DP8520A21A22A

through the Address Bus and an IO Port

Another simple way the chip can be programmed is the first

write after system reset This method requires only a flip-

flop and an OR gate as shown in

Figure 50 At reset the flip-

flop is preset which pulls the Q output low Since WR is

negated ML is not enabled The first write access is used to

program the chip When WR is asserted ML is asserted

WR negated clocks the flip-flop negates ML and programs

the DP8520A21A22A with the address and ECAS0 avail-

able at that time CS does not need to be asserted using

this method

TLF9338 – A1

FIGURE 50 Programming the DP8520A21A22A on the First CPU Write after Power Up

DP8500 Datasheet(PDF) 38 Page - National Semiconductor (TI)