DP8500 datasheet(46/70 Pages) NSC

Part #	DP8500

Description	DP8520A/DP8521A/DP8522A microCMOS Programmable 256k/1M/4M Video RAM Controller/Drivers

PDF	70 Pages

Scroll/Zoom	100%

Manufacturer	NSC [National Semiconductor (TI)]

Direct Link	http://www.national.com

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46 / 70 page

120 Dual Accessing Functions (DP8522A) (Continued)

Since the DP8522A has only one set of address inputs the

signal is used with the addition of buffers to allow the cur-

rently granted port’s addresses to reach the DP8522A The

signals which need to be bufferred are R0 – 10 C0 – 10

B0 – 1 ECAS0 – 1 and LOCK All other inputs are not com-

mon and do not have to be buffered as shown in

Figure 58a

If a Port which is not currently granted tries to access

the VRAM array the GRANTB output will transition from a

rising clock edge from AREQ or AREQB negating and will

preceed the RAS for the access by one or two clock peri-

ods GRANTB will then stay in this state until the other port

requests an access and the currently granted port is not

accessing the VRAM as shown in

Figure 58b

Dual Accessing Using the DP8522A

TLF9338 – 1

If Port B is synchronous the Request Synchronizing logic will not be required

FIGURE 58a Dual Accessing Using the DP8522A to interface a CPU and a Graphics Processor to a Video RAM System

DP8500 Datasheet(PDF) 46 Page - National Semiconductor (TI)