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DP8500 Datasheet(PDF) 31 Page - National Semiconductor (TI) |
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DP8500 Datasheet(HTML) 31 Page - National Semiconductor (TI) |
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31 / 70 page ![]() 70 Additional Access Support Features 73 DELAY CAS DURING WRITE ACCESSES Address bit C9 asserted during programming will cause CAS to be delayed until the first positive edge of CLK after RAS is asserted when the input WIN is asserted Delaying CAS during write accesses ensures that the data to be written to VRAM will be setup to CAS asserting as shown in Figures 34 and 35 If the possibility exists that data still may not be present after the first positive edge of CLK CAS can be delayed further with the ECAS inputs If address bit C9 is negated during programming read and write accesses will be treated the same (with regard to CAS) TLF9338 – 85 FIGURE 34 Mode 0 Delay CAS TLF9338 – 86 FIGURE 35 Mode 1 Delay CAS 31 |
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