DP8500 datasheet(52/70 Pages) NSC

52 / 70 page

150 AC Timing Parameters DP8520ADP8521ADP8522A (Continued)

Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 VRAMs

per bank including trace capacitance (see Note 2)

Two different loads are specified

CL e 50 pF loads on all outputs except

CL e 150 pF loads on Q0–8 9 and 10 or

CH e 50 pF loads on all outputs except

CH e 125 pF loads on RAS0–3 and CAS0–3 and

CH e 380 pF loads on Q0–8 9 and 10

Common Dual Access

8520A21A22A-25

Number

Symbol

Parameter Description

Min

Max

Min

Max

100

tHCKARQB

AREQB Negated Held from CLK High

101

tSARQBCK

AREQB Asserted Setup to CLK High

102

tPAQBRASL

AREQB Asserted to RAS Asserted

103

tPAQBRASH

AREQB Negated to RAS Negated

105

tPCKRASG

CLK High to RAS Asserted for

Pending Port B Access

106

tPAQBATKBL

AREQB Asserted to ATACKB Asserted

107

tPCKATKB

CLK High to ATACKB Asserted

for Pending Access

108

tPCKGH

CLK High to GRANTB Asserted

109

tPCKGL

CLK High to GRANTB Negated

110

tSADDCKG

Row Address Setup to CLK High That

Asserts RAS following a GRANTB

Change to Ensure tASR e 0 ns for Port B

111

tSLOCKCK

LOCK Asserted Setup to CLK Low

to Lock Current Port

112

tPAQATKBH

AREQ Negated to ATACKB Negated

113

tPAQBCASH

AREQB Negated to CAS Negated

114

tSADAQB

Address Valid Setup to

712

AREQB Asserted

116

tHCKARQG

AREQ Negated Held from CLK High

117

tWAQB

AREQB High Pulse Width

to Guarantee tASR e 0ns

118a

tPAQBCAS0

AREQB Asserted to CAS Asserted

(tRAH e 15 ns tASC e 0 ns)

118b

tPAQBCAS1

AREQB Asserted to CAS Asserted

104

(tRAH e 15 ns tASC e 10 ns)

118c

tPAQBCAS2

AREQB Asserted to CAS Asserted

104

(tRAH e 25 ns tASC e 0 ns)

118d

tPAQBCAS3

AREQB Asserted to CAS Asserted

107

114

(tRAH e 25 ns tASC e 10 ns)

120a

tPCKCASG0

CLK High to CAS Asserted

for Pending Port B Access

103

(tRAH e 15 ns tASC e 0 ns)

120b

tPCKCASG1

CLK High to CAS Asserted

for Pending Port B Access

106

113

(tRAH e 15 ns tASC e 0 ns)

120c

tPCKCASG2

CLK High to CAS Asserted

for Pending Port B Access

106

113

(tRAH e 25 ns tASC e 0 ns)

120d

tPCKCASG3

CLK High to CAS Asserted

for Pending Port B Access

116

123

(tRAH e 25 ns tASC e 10 ns)

121

tSBADDCKG

Bank Address Valid Setup to CLK

High That Starts RAS

for Pending Port B Access

DP8500 Datasheet(PDF) 52 Page - National Semiconductor (TI)

DP8500 Datasheet(HTML) 52 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Download

Link URL