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DP8500 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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DP8500 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 70 page  TLF9338 PRELIMINARY May 1992 DP8520ADP8521ADP8522A microCMOS Programmable 256k1M4M Video RAM ControllerDrivers General Description The DP8520A21A22A video RAM controllers provide a low cost single chip interface between video RAM and all 8- 16- and 32-bit systems The DP8520A21A22A gener- ate all the required access control signal timing for VRAMs An on-chip refresh request clock is used to automatically refresh the VRAM array Refreshes and accesses are arbi- trated on chip If necessary a WAIT or DTACK output in- serts wait states into system access cycles including burst mode accesses RAS low time during refreshes and RAS precharge time after refreshes and back to back accesses are guaranteed through the insertion of wait states Sepa- rate on-chip precharge counters for each RAS output can be used for memory interleaving to avoid delayed back to back accesses because of precharge An additional feature of the DP8522A is two access ports to simplify dual access- ing Arbitration among these ports and refresh is done on chip Features Y On chip high precision delay line to guarantee critical VRAM access timing parameters Y microCMOS process for low power Y High capacitance drivers for RAS CAS DT OE and VRAM address on chip Y On chip support for nibble page and static column VRAMs Y Byte enable signals on chip allow byte writing in a word size up to 16 bits with no external logic Y Selection of controller speeds 20 MHz and 25 MHz Y On board Port APort B (DP8522A only)refresh arbitra- tion logic Y Direct interface to all major microprocessors (applica- tion notes available) Y 4 RAS and 4 CAS drivers (the RAS and CAS configura- tion is programmable) of Pins of Address Largest Direct Drive Access Control (PLCC) Outputs VRAM Memory Ports Possible Capacity Available DP8520A 68 9 256 kbit 4 Mbytes Single Access Port DP8521A 68 10 1 Mbit 16 Mbytes Single Access Port DP8522A 84 11 4 Mbit 64 Mbytes Dual Access Ports (A and B) Block Diagram DP8520A21A22A VRAM Controller TLF9338 – 5 FIGURE 1 TRI-STATE is a registered trademark of National Semiconductor Corporation PAL is a registered trademark of and is used under license from Monolithic Memories Inc C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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