DP8500 datasheet(35/70 Pages) NSC

Part #	DP8500

Description	DP8520A/DP8521A/DP8522A microCMOS Programmable 256k/1M/4M Video RAM Controller/Drivers

PDF	70 Pages

Scroll/Zoom	100%

Manufacturer	NSC [National Semiconductor (TI)]

Direct Link	http://www.national.com

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35 / 70 page

80 RAS and CAS Configuration Modes (Continued)

TLF9338 – 91

FIGURE 40 VRAM Array Setup for 4 Banks Using Address Pipelining (C6 C5 C4 e 1 1 1

or C6 C5 C4 e 0 1 0 (Also Allowing Error Scrubbing) during Programming)

TLF9338 – 92

FIGURE 41 VRAM Array Setup for Address Pipelining with 2 Banks (C6 C5 C4 e 1 0 1

or C6 C5 C4 e 0 0 1 (Also Allowing Error Scrubbing) during Programming)

84 ERROR SCRUBBING

In error scrubbing during refresh the user selects one two

or four RAS and CAS outputs per bank When performing

error detection and correction memory is always accessed

as words Since the CAS signals are not used to select

individual bytes their corresponding ECAS inputs can be

tied low as shown in

Figures 42 and 43

TLF9338 – 93

FIGURE 42 VRAM Array Setup for 4 Banks Using Error Scrubbing (C6 C5 C4 e 0 1 0 during Programming)

TLF9338 – 94

FIGURE 43 VRAM Array Setup for Error Scrubbing with 2 Banks (C6 C5 C4 e 0 0 1 during Programming)

DP8500 Datasheet(PDF) 35 Page - National Semiconductor (TI)