DP8500 datasheet(13/70 Pages) NSC

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40 Refresh Options

The DP8520A21A22A support a wide variety of refresh

control mode options including automatic internally con-

trolled refresh externally controlledburst refresh refresh

requestacknowledge and any combination of the above

With each of the control modes above different types of

refreshes can be performed These different types include

all RAS refresh staggered refresh and error scrubbing dur-

ing all RAS refresh

There are three inputs EXTNDRF RFSH and DISRFSH

and one output RFIP (RFRQ) associated with refresh

There are also ten programming bits R0 – 1 R9 C0 – 6 and

ECAS0 used to program the various types of refreshing

The two inputs RFSH and DISRFSH are used in the exter-

nally controlledburst refresh mode and the refresh re-

questacknowledge mode The output RFRQ is used in the

refresh requestacknowledge mode The input EXTNDRF is

used in all refresh modes and the output RFIP is used in all

refresh modes except the refresh requestacknowledge

mode Asserting the input EXTNDRF extends the refresh

cycle single or multiple integral clock periods of CLK The

output RFIP is asserted one period of CLK before the first

refresh RAS is asserted If an access is currently in prog-

ress RFIP will be asserted up to one period of CLK before

the first refresh RAS once AREQ or AREQB is negated for

the access (see

Figure 7a )

The DP8520A21A22A will increment the refresh address

counter automatically independent of the refresh mode

used The refresh address counter will be incremented once

all the refresh RASs have been negated

In every combination of refresh control mode and refresh

type the DP8520A21A22A is programmed to keep RAS

asserted a number of CLK periods The values of RAS low

time during refresh are programmed with the programming

bits R0 and R1

41 REFRESH CONTROL MODES

There are three different modes of refresh control Any of

these modes can be used in combination or singularly to

produce the desired refresh results The three different

modes of control are automatic internal refresh external

burst refresh and refresh requestacknowledge

411 Automatic Internal Refresh

The DP8520A21A22A have an internal refresh clock The

period of the refresh clock is generated from the program-

ming bits C0 – 3 Every period of the refresh clock an inter-

nal refresh request is generated As long as a VRAM access

is not currently in progress and precharge time has been

met the internal refresh request will generate an automatic

internal refresh If a VRAM access is in progress the

DP8520A21A22A on-chip arbitration logic will wait until

the access is finished before performing the refresh The

refreshaccess arbitration logic can insert a refresh cycle

between two address pipelined accesses However the re-

fresh arbitration logic can not interrupt an access cycle to

perform a refresh To enable automatic internally controlled

refreshes the input DISRFSH must be negated

412 Externally ControlledBurst Refresh

To use externally controlledburst refresh the user must

disable the automatic internally controlled refreshes by as-

serting the input DISRFSH The user is responsible for gen-

erating the refresh request by asserting the input RFSH

Pulsing RFSH low sets an internal latch that is used to

produce the internal refresh request The refresh cycle will

take place on the next positive edge of CLK as shown in

Figure 7b If an access to VRAM is in progress or precharge

time for the last access has not been met the refresh will be

delayed Since pulsing RFSH low sets a latch the user does

not have to keep RFSH low until the refresh starts When

the last refresh RAS negates the internal refresh request

latch is cleared

By keeping RFSH asserted past the positive edge of CLK

which ends the refresh cycle as shown in

Figure 8 the user

will perform another refresh cycle Using this technique the

user can perform a burst refresh consisting of any number

of refresh cycles Each refresh cycle during a burst refresh

will meet the refresh RAS low time and the RAS precharge

time (programming bits R0 – 1)

If the user desires to burst refresh the entire VRAM (all row

addresses) he could generate an end of count signal (burst

refresh finished) by looking at one of the DP8520A21A

22A high address outputs (Q7 Q8 Q9 or Q10) and the RFIP

output The Qn outputs function as a decode of how many

row addresses have been refreshed (Q7 e 128 refreshes

Q8 e 256 refreshes Q9 e 512 refreshes Q10 e 1024

refreshes)

413 Refresh RequestAcknowledge

The DP8520A21A22A can be programmed to output in-

ternal refresh requests When the user programs ECAS0

negated during programming the RFIP output functions as

RFRQ RFRQ will be asserted from a positive edge of CLK

as shown in

Figure 9a Once RFRQ is asserted it will stay

asserted until the RFSH is pulsed low with DISRFSH assert-

ed This will cause an externally requestedburst refresh to

take place If DISRFSH is negated an automatic internal

refresh will take place as shown in

Figure 9b

RFRQ will go high and then assert if additional periods of

the internal refresh clock have expired and neither an exter-

nally controlled refresh nor an automatically controlled inter-

nal refresh have taken place as shown in

Figure 9c If a time

critical event or long access like pagestatic column mode

access can not be interrupted RFRQ pulsing high can be

used to increment a counter The counter can be used to

perform a burst refresh of the number of refreshes missed

(through the RFSH input)

42 REFRESH CYCLE TYPES

Three different types of refresh cycles are available for use

The three different types are mutually exclusive and can be

used with any of the three modes of refresh control The

three different refresh cycle types are all RAS refresh stag-

gered RAS refresh and error scrubbing during all RAS re-

fresh In all refresh cycle types the RAS precharge time is

guaranteed between the previous access RAS ending and

the refresh RAS0 starting between refresh RAS3 ending

and access RAS beginning between burst refresh RASs

421 Conventional RAS Refresh

A conventional refresh cycle causes RAS0 – 3 to all assert

from the first positive edge of CLK after RFIP is asserted as

shown in

Figure 10 RAS0 – 3 will stay asserted until the

number of positive edges of CLK programmed have passed

On the last positive edge RAS0 – 3 and RFIP will be negat-

ed This type of refresh cycle is programmed by negating

address bit R9 during programming

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