DP8500 datasheet(45/70 Pages) NSC

45 / 70 page

120 Dual Accessing Functions (DP8522A) (Continued)

122 PORT B WAIT STATE SUPPORT (DP8522A)

Advanced transfer acknowledge for Port B ATACKB is

used for wait state support for Port B This output will be

asserted when RAS for the Port B access is asserted as

shown in

Figures 55 and 56 Once asserted this output will

stay asserted until AREQB is negated With external logic

ATACKB can be made to interface to any CPU’s wait input

as shown in

Figure 57

TLF9338 – A8

A) Extend ATACK to

Clock) after RAS goes low

TLF9338 – A9

B) Extend ATACK to 1T after RAS goes low

TLF9338 – B0

C) Synchronize ATACKB to CPU B Clock This is useful if CPU B runs asyn-

chronous to the DP8522

FIGURE 57 Modifying Wait Logic for Port B

123 COMMON PORT A AND PORT B DUAL PORT

FUNCTIONS

An input LOCK and an output GRANTB add additional

functionality to the dual port arbitration logic LOCK allows

Port A or Port B to lock out the other port from the VRAM

When a Port is locked out of the VRAM wait states will be

inserted into its access cycle until it is allowed to access

memory GRANTB is used to multiplex the input control sig-

nals and addresses to the DP8522A

1231 GRANTB Output

The output GRANTB determines which port has current ac-

cess to the VRAM array GRANTB asserted signifies Port B

has access GRANTB negated signifies Port A has access

to the VRAM array

TLF9338 – B1

FIGURE 55 Non-Delayed Port B Access

TLF9338 – B2

FIGURE 56 Delayed Port B Access

DP8500 Datasheet(PDF) 45 Page - National Semiconductor (TI)