DP8500 datasheet(40/70 Pages) NSC

40 / 70 page

90 Programming and Resetting (Continued)

94 PROGRAMMING BIT DEFINITIONS

Symbol

Description

ECAS0

Extend CAS Refresh Request Select

The CASn outputs will be negated with the RASn outputs when AREQ (or AREQB DP8522A only) is

negated The RFIP pin will function as refresh in progress During a video shift register load operation the

DT OE output will be negated by either the 4th rising clock edge after the input VSRL asserts or by the

VSRL input negating whichever occurs first when this mode is programmed

The CASn outputs will be negated during an access (Port A (or Port B DP8522A only)) when their

corresponding ECASn inputs are negated This feature allows the CAS outputs to be extended beyond the

RAS outputs negating Scrubbing refreshes are NOT affected During scrubbing refreshes the CAS outputs

will negate along with the RAS outputs regardless of the state of the ECAS inputs

The RFIP output will function as ReFresh ReQuest (RFRQ) when this mode is programmed The DT OE

output will be negated by the input VSRL negating when this mode is programmed

Access Mode Select

ACCESS MODE 0

ALE pulsing high sets an internal latch On the next positive edge of CLK the access

(RAS) will start AREQ will terminate the access

ACCESS MODE 1

ADS asserted starts the access (RAS) immediately AREQ will terminate the access

Address Latch Mode

ADS or ALE asserted for Port A or AREQB asserted for Port B with the appropriate GRANT latch the input

row column and bank address

The row column and bank latches are fall through

Delay CAS during WRITE Accesses

CAS is treated the same for both READ and WRITE accesses

During WRITE accesses CAS will be asserted by the event that occurs last CAS asserted by the internal

delay line or CAS asserted on the positive edge of CLK after RAS is asserted

Row Address Hold Time

Row Address Hold Time e 25 ns minimum

Row Address Hold Time e 15 ns minimum

Column Address Setup Time

Column Address Setup Time e 10 ns minimum

Column Address Setup Time e 0 ns minimum

C6 C5 C4

RAS and CAS Configuration ModesError Scrubbing during Refresh

0 0 0

RAS0 – 3 and CAS0 – 3 are all selected during an access For a particular CAS to be asserted its

corresponding ECAS input must be asserted B0 and B1 are not used during an access Error scrubbing

during refresh

0 0 1

RAS and CAS pairs are selected during an access by B1 For a particular CAS to be asserted its

corresponding ECAS input must be asserted

B1 e 0 during an access selects RAS0 – 1 and CAS0–1

B1 e 1 during an access selects RAS2 – 3 and CAS2–3

B0 is not used during an Access

Error scrubbing during refresh

0 1 0

RAS and CAS singles are selected during an access by B0 – 1 For a particular CAS to be asserted its

corresponding ECAS input must be asserted

B1 e 0 B0 e 0 during an access selects RAS0 and CAS0

B1 e 0 B0 e 1 during an access selects RAS1 and CAS1

B1 e 1 B0 e 0 during an access selects RAS2 and CAS2

B1 e 1 B0 e 1 during an access selects RAS3 and CAS3

Error scrubbing during refresh

0 1 1

RAS0 – 3 and CAS0 – 3 are all selected during an access For a particular CAS to be asserted its

corresponding ECAS input must be asserted

B1 B0 are not used during an access

No error scrubbing (RAS only refreshing)

DP8500 Datasheet(PDF) 40 Page - National Semiconductor (TI)

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