DP8500 datasheet(57/70 Pages) NSC

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150 AC Timing Parameters DP8520ADP8521ADP8522A (Continued)

Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 VRAMs

per bank including trace capacitance (see Note 2)

Two different loads are specified

CL e 50 pF loads on all outputs except

CL e 150 pF loads on Q0–8 9 and 10 or

CH e 50 pF loads on all outputs except

CH e 125 pF loads on RAS0–3 and CAS0–3 and

CH e 380 pF loads on Q0–8 9 and 10

Programing

8520A21A22A-25

Number

Symbol

Parameter Description

Min

Max

Min

Max

500

tHMLADD

Mode Address Held from ML Negated

501

tSADDML

Mode Address Setup to ML Negated

502

tWML

ML Pulse Width

503

tSADAQML

Mode Address Setup to AREQ Asserted

504

tHADAQML

Mode Address Held from AREQ Asserted

505

tSCSARQ

CS Asserted Setup to

AREQ Asserted

506

tSMLARQ

ML Asserted Setup to AREQ Asserted

600

tSCKVSRL

VSRL Low Setup to CLK Rising Edge to

guarantee counting VSRL as being Low

(used to determine when to end Graphics

Shift load access)

601

tHVSRLCK

VSRL Low from CLK High (to guarantee

VSRL is not counted as being Low until

the next rising clock edge)

602

tSCKAVSRL

AVSRLRQ Low before CLK Rising Edge

to guarantee locking the VRAM to only

Port A accesses

603

tPVSRLDTL

VSRL Low to DT OE Low during

Graphics Shift Register Load access

604

tPVSRLDTH

VSRL Negated to DT OE Negated

605

tPCKDTL

CLK to DT OE Negated

Note 1

‘‘Absolute Maximum Ratings’’ are the values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the device

should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation

Note 2

Input pulse 0V to 3V tR e tF e 25 ns Input reference point on AC measurements is 15V Output reference points are 24V for High and 08V for Low

Note 3

AC Production testing is done at 50 pF

DP8500 Datasheet(PDF) 57 Page - National Semiconductor (TI)

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