DP8500 datasheet(3/70 Pages) NSC

3 / 70 page

10 Introduction

The DP8520A21A22A are CMOS Video RAM controllers

that incorporate many advanced features including the ca-

pabilities of address latches refresh counter refresh clock

row column and refresh address multiplexor delay line re-

freshaccessVRAM transfer cycle arbitration logic and

high capacitive drivers The programmable system interface

allows any manufacturer’s microprocessor or bus to directly

interface via the DP8520A21A22A to VRAM arrays up to

64 Mbytes in size

After power up the DP8520A21A22A must first be pro-

grammed before accessing the VRAM The chip is pro-

grammed through the address bus

There are two methods of programming the chip The first

method mode load only is accomplished by asserting the

signal mode load ML A valid programming selection is pre-

sented on the row column bank and ECAS inputs then ML

is negated When ML is negated the chip is programmed

with the valid programming bits on the address bus

The second method chip selected access is accomplished

by asserting ML and performing a chip selected access

When CS and AREQ are asserted for the access the chip is

programmed During this programming access the pro-

gramming bits affecting the wait logic become effective im-

mediately allowing the access to terminate After the ac-

cess ML is negated and the rest of the programming bits

take effect

Once the DP8520A21A22A has been programmed a

60 ms initialization period is entered During this time the

DP8520A21A22A controllers perform refreshes to the

VRAM array so further VRAM warm up cycles are unneces-

sary

The DP8520A21A22A can now be used to access the

VRAM There are two modes of accessing with the control-

ler The two modes are Mode 0 which initiates RAS syn-

chronously and Mode 1 which initiates RAS asynchronous-

To access the VRAM using Mode 0 the signal ALE is as-

serted along with CS to ensure a valid VRAM access ALE

asserting sets an internal latch and only needs to be pulsed

and not held throughout the entire access On the next ris-

ing clock edge after the latch is set RAS will be asserted

for that access The DP8520A21A22A will place the row

address on the VRAM address bus guarantee the pro-

grammed value of row address hold time of the VRAM

place the column address on the VRAM address bus guar-

antee the programmed value of column address setup time

and assert CAS AREQ can be asserted anytime after the

clock edge which starts the access RAS RAS and CAS will

extend until AREQ is negated

The other access mode Mode 1 is asynchronous to the

clock

When ADS is asserted

RAS is asserted

The

DP8520A21A22A will place the row address on the

VRAM address bus guarantee the programmed value of

row address hold time place the column address on the

VRAM address bus guarantee the programmed value of

column address setup time and assert CAS AREQ can be

tied to ADS or can be asserted after ADS is asserted AREQ

negated will terminate the access

The DP8520A21A22A also provides full support for

VRAM transfer cycles

To begin the cycle

the input

AVSRLRQ Advanced Video Shift Register Load Request is

asserted and must precede the input VSRL Video Shift

tee any access in progress or pending refresh can finish

VSRL asserting causes DT OE to transition low immediate-

ly Both VSRL and DT OE assert before RAS and CAS as-

sert for the transfer The cycle is ended by DT OE negating

This is caused by either VSRL negating or by four rising

edges of CLK from VSRL asserting whichever comes first

The DP8520A21A22A have greatly expanded refresh ca-

pabilities compared to other VRAM controllers There are

three modes of refreshing available These modes are inter-

nal automatic refreshing

externally controlledburst re-

freshing and refresh requestacknowledge refreshing Any

of these modes can be used together or separately to

achieve the desired results In any combination of these

modes the programming of ECAS0 determines the use of

the RFIP (RFRQ) pin ECAS0 asserted during programming

causes this pin to function as RFIP which will assert just

prior to a refresh cycle and will negate when the refresh is

completed ECAS0 negated during programming causes

this pin to function as RFRQ which indicates an internal

refresh request when asserted

When using internal automatic refreshing the DP8520A

21A22A will generate an internal refresh request from the

refresh request clock The DP8520A21A22A will arbitrate

between the refresh requests and accesses Assuming an

access is not currently in progress the DP8520A21A22A

will grant a refresh assert RFIP if programmed and on the

next positive clock edge refreshing will begin If an access

had been in progress the refresh will begin after the access

has terminated

To use externally controlledburst refresh the user disables

the

internal

refresh

request

asserting

the

input

DISRFRSH A refresh can now be externally requested by

asserting the input RFSH The DP8520A21A22A will arbi-

trate between the external refresh request and accesses

Assuming an access is not currently in progress

the

DP8520A21A22A will grant a refresh assert RFIP if pro-

grammed and on the next positive clock edge refreshing

will begin If an access had been in progress the refresh

would take place after the access has terminated

With refresh requestacknowledge mode the DP8520A

21A22A broadcasts the internal refresh request to the sys-

tem through the RFRQ output pin External circuitry can de-

termine when to refresh the VRAM through the RFSH input

The controllers have three types of refreshing available

conventional staggered and error scrubbing Any refresh

control mode can be used with any type of refresh In a

conventional refresh all of the RAS outputs will be asserted

and negated at once In a staggered refresh the RAS out-

puts will be asserted one positive clock edge apart Error

scrubbing is the same as conventional refresh except that a

CAS will be asserted during a refresh allowing the system to

run that data through an EDAC chip and write it back to

memory if a single bit error has occurred The refreshes

can be extended with the EXTEND REFRESH input

EXTNDRF

The DP8520A21A22A have wait support available as

DTACK or WAIT Both are programmable DTACK Data

Transfer ACKnowledge is useful for processors whose wait

signal is active high WAIT is useful for processors whose

DP8500 Datasheet(PDF) 3 Page - National Semiconductor (TI)

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