DP8500 datasheet(26/70 Pages) NSC

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60 DP8520A21A22A Video RAM Support (Continued)

During a transfer cycle (VSRL asserted during the access)

WIN is disabled from affecting the DT OE logic until the

transfer cycle is completed as shown by CAS negating Dur-

ing a transfer cycle the SOE (Serial Output Enable) input to

the VRAM is asserted and is used as an output control for a

read transfer cycle and is used as a write enable control

during a write transfer cycle When SOE is negated serial

access is disabled and a transfer cycle cannot take place

SOE asserted during a read enables the serial inputoutput

bus SIO (0 – 3) while the VRAM data bus (DQ0 – 3) is put

into a high impedance state thus allowing the transfer cycle

to take place from the serial port In addition to both read

and write transfer cycles the DP8520A21A22A also sup-

ports pseudo write transfer cycles (see

Figure 26 ) A pseu-

do write transfer cycle must be performed after a read trans-

fer cycle if the subsequent operation is a write transfer cy-

cle The DP8520A21A22A VRAM controller is operated

as if it is doing a write transfer cycle but since the SOE input

to the VRAM is negated (disabling the serial port) a transfer

doesn’t take place The purpose of this pseudo write trans-

fer cycle is to switch the SIO (0 – 3) lines of the VRAM’s

serial port from output mode to input mode

TLF9338 – 79

FIGURE 26 Video RAM Timing Pseudo WRITE Transfer Cycle B Port Active

(Transfer Shift Register Data into VRAM Row)

DP8500 Datasheet(PDF) 26 Page - National Semiconductor (TI)