DP8500 datasheet(42/70 Pages) NSC

42 / 70 page

90 Programming and Resetting (Continued)

94 PROGRAMMING BIT DEFINITIONS

(Continued)

Symbol

Description

WAIT or DTACK Select

WAIT type output is selected

DTACK (Data Transfer ACKnowledge) type output is selected

Add Wait States to the Current Access if WAITIN is Low

WAIT or DTACK will be delayed by one additional positive edge of CLK

WAIT or DTACK will be delayed by two additional positive edges of CLK

R5 R4

WAIT DTACK during Burst (See Section 512 or 522)

0 0

NO WAIT STATES If R7 e 0 during programming WAIT will remain negated during burst portion of access

If R7 e 1 programming DTACK will remain asserted during burst portion of access

0 1

1T If R7 e 0 during programming WAIT will assert when the ECAS inputs are negated with AREQ asserted

WAIT will negate from the positive edge of CLK after the ECASs have been asserted

If R7 e 1 during programming DTACK will negate when the ECAS inputs are negated with AREQ asserted

DTACK will assert from the positive edge of CLK after the ECASs have been asserted

1 0

T If R7 e 0 during programming WAIT will assert when the ECAS inputs are negated with AREQ

asserted WAIT will negate on the negative level of CLK after the ECASs have been asserted

If R7 e 1 during programming DTACK will negate when the ECAS inputs are negated with AREQ asserted

DTACK will assert from the negative level of CLK after the ECASs have been asserted

1 1

0T If R7 e 0 during programming WAIT will assert when the ECAS inputs are negated WAIT will negate

when the ECAS inputs are asserted

If R7 e 1 during programming DTACK will negate when the ECAS inputs are negated DTACK will assert

when the ECAS inputs are asserted

R3 R2

WAIT DTACK Delay Times (See Section 511 or 521)

0 0

NO WAIT STATES If R7 e 0 during programming WAIT will remain high during non-delayed accesses

WAIT will negate when RAS is negated during delayed accesses

NO WAIT STATES If R7 e 1 during programming DTACK will be asserted when RAS is asserted

0 1

T If R7 e 0 during programming WAIT will negate on the negative level of CLK after the access RAS

1T If R7 e 1 during programming DTACK will be asserted on the positive edge of CLK after the access

RAS

1 0

NO WAIT STATES

T If R7 e 0 during programming WAIT will remain high during non-delayed accesses

WAIT will negate on the negative level of CLK after the access RAS during delayed accesses

T If R7 e 1 during programming DTACK will be asserted on the negative level of CLK after the access

RAS

1 1

1T If R7 e 0 during programming WAIT will negate on the positive edge of CLK after the access RAS

T If R7 e 1 during programming DTACK will be asserted on the negative level of CLK after the positive

edge of CLK after the access RAS

R1 R0

RAS Low and RAS Precharge Time

0 0

RAS asserted during refresh e 2 positive edges of CLK

RAS precharge time e 1 positive edge of CLK

RAS will start from the first positive edge of CLK after GRANTB transitions (DP8522A)

0 1

RAS asserted during refresh e 3 positive edges of CLK

RAS precharge time e 2 positive edges of CLK

RAS will start from the second positive edge of CLK after GRANTB transitions (DP8522A)

1 0

RAS asserted during refresh e 2 positive edges of CLK

RAS precharge time e 2 positive edges of CLK

RAS will start from the first positive edge of CLK after GRANTB transitions (DP8522A)

1 1

RAS asserted during refresh e 4 positive edges of CLK

RAS precharge time e 3 positive edges of CLK

RAS will start from the second positive edge of CLK after GRANTB transitions (DP8522A)

Note 1

The configuration modes allow RASs and CASs to be grouped such that each RAS and CAS will drive one-fourth of the total VRAM array whether the array

is organized as 1 2 or 4 banks

Note 2

In order for a CAS output to go low during an access it must be both selected and enabled ECAS0–1 are used to enable the CAS outputs (ECAS0 enables

CAS01 ECAS1 enables CAS23) Selection is determined by the configuration mode and B1 B0

DP8500 Datasheet(PDF) 42 Page - National Semiconductor (TI)

DP8500 Datasheet(HTML) 42 Page - National Semiconductor (TI)

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